Ultra sensitive silicon sensor readout circuitry

ABSTRACT

A readout circuit for a bolometer type sensor including a pair of back-to-back temperature sensing diodes connected in an electro-thermal feedback loop including a semiconductor amplifier circuit located in an intermediate stage between a detector stage and a heat bath stage and wherein the heat generated by the amplifier equalizes the temperature between the intermediate stage and the detector stage. The readout circuitry also includes circuitry for removing local threshold voltage variations and low frequency 1/f noise components in the readout signal while providing high temperature sensitivity and relatively high voltage gain.

CLAIM OF PRIORITY

This application is a Non-Provisional application including the subjectmatter and claiming the priority date Under 35 U.S.C. §119(e) ofProvisional application Ser. No. 60/614,050, filed Sep. 30, 2004, thecontents of which are meant to be incorporated herein by reference.

RELATED APPLICATIONS

This application is related to Non-Provisional application Ser. No.______ (Northrop Grumman Ref. No. 000800-078), entitled “SensitiveSilicon Sensor And Test Structure For An Ultra-Sensitive Silicon Sensor”filed on ______, 2005; Non-Provisional application Ser. No. ______(Northrop Grumman Ref. No. 000775-078), entitled “Focal Plane Antenna ToSensor Interface For An Ultra-Sensitive Silicon Sensor” filed on ______,2005; and Non-Provisional application Ser. No. ______ (Northrop GrummanRef. No. 000801-078), entitled “Low Noise Field Effect Transistor”,filed on ______, 2005.

CROSS REFERENCE TO RELATED ART

This application is also related to U.S. Pat. No. 6,489,615 entitled“Ultra-Sensitive Silicon Sensor”, granted to Nathan Bluzer, the presentinventor, on Dec. 3, 2002, and assigned to the assignee of thisinvention. U.S. Pat. No. 6,489,615 is intended to be incorporated hereinby reference for any and all purposes.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to bolometer type radiation sensors fordetecting thermal radiation and more particularly to circuitry forproviding a readout signal of a bolometer sensor.

2. Related Art

Bolometers are well known in the art and comprise devices which generatea voltage output when thermal radiation is absorbed. These devices havebeen successfully used for infra-red (IR) imaging in the long waveinfra-red (LWIR) band of the electromagnetic spectrum. Extending thesedevices to other spectral bands has proven relatively difficult in thepast. However, efforts are currently under way to extend this capabilityto millimeter wave (mm) and terahertz (THz) spectral bands and thusthere is a need for imagers operating in the mm and THz spectral bands.Applications for such devices include, for example, multi-spectralimaging for improved navigation, target recognition and detection aswell as homeland defense applications. Such applications all require theuse of bolometers. Therefore, realizing bolometers with acceptableperformance with mm-THZ-LWIR cameras requires the formulation of newapproaches for overcoming conventional limitations such as therequirement for faster response time and the ability to maintainsensitivity for relatively long periods. Moreover, fast response timedictates minimizing the mass of the bolometer's absorbing element.

In related application Ser. No. ______ (Northrop Grumman Ref. No.000800-078), entitled “Sensitive Silicon Sensor And Test Structure ForAn Ultra-Sensitive Silicon Sensor”, there is disclosed a sensor ofthermal radiation comprised of a pair of silicon diodes connected inback-to-back relationship with one of the diodes being located in adetector stage, while the other diode is located in a heat bath stagealong with a temperature difference amplifier. The detector stage isthermally isolated from the heat bath stage by a low thermalconductivity link which includes electrical wiring for connecting theback-to-back diodes.

In related application Ser. No. ______ (Northrop Grumman Ref. No.000775-078), entitled “Focal Plane Antenna To Sensor Interface For AnUltra-Sensitive Silicon Sensor”, there is disclosed an electricalinterface between a scene to be imaged, and a bolometer type sensorlocated, for example in a pixel, and wherein the efficiency of eachpixel is improved by means of a thermal energy concentrator including alens and an antenna. Where a plurality of pixels are located in anarray, a microantenna is provided for each pixel in the array with acommon lens being provided to focus and channel incoming radiation toeach microantenna. Radiation from a scene is further coupled by means ofa lens and microantenna to the absorbing element of each bolometerthrough an AC coupling circuit including an electronic chopperimplemented by means of a PIN diode, the conductivity of which is variedso as to affect the reflection coefficient of the input signal suppliedthrough the microantenna.

In U.S. Pat. No. 6,489,615, there is disclosed in a pair of back-to-backtemperature sensing silicon diodes respectively located in a detectorstage and an intermediate stage and coupled to a temperature differenceamplifier also located in the intermediate stage. The intermediate stageis located between the detector stage and the heat bath stage, with theintermediate stage also including an electro-thermal feedback loop whichis provided by the heat generated by an amplifier located in theintermediate stage which generates heat which is proportional to thetemperature difference between the difference between the detectedtemperatures provided by the silicon diodes. The heat provided by theamplifier acts to actively zero the temperature difference between thedetector and the intermediate stage so as to eliminate any net heat flowbetween the detector element and the intermediate stage.

SUMMARY

It is an object of the present invention to provide sensor readoutcircuitry for a bolometer type sensor and wherein the sensor includes apair of back-to-back temperature sensing diodes connected in anelectro-thermal feedback loop including a semiconductor amplifiercircuit located in an intermediate stage between a detector stage and aheat bath stage and wherein the heat generated by the amplifierequalizes the temperature between the intermediate stage and thedetector stage. The readout circuitry also includes circuitry forproviding cancellation of local threshold voltage variations and of lowfrequency 1/f noise components while providing high temperaturesensitivity and relatively high voltage gain.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will become more fully understood from thedetailed description described hereinafter and the accompanying drawingswhich are provided by way of illustration only, and thus are not meantto be considered in a limiting sense, and wherein:

FIG. 1 is a cross section of a related art ultra-sensitive siliconsensor;

FIG. 2 is an electrical schematic diagram illustrative ofelectro-thermal feedback circuit implemented in the embodiment of thesensor shown in FIG. 1;

FIG. 3 is an electrical schematic diagram further illustrative of theembodiment shown in FIG. 1;

FIG. 4 is an electrical band diagram of a single silicon p-n junction;

FIG. 5A is illustrative of a pair of silicon diodes connected inback-to-back circuit relationship;

FIG. 5B is a band diagram illustrative of the back-to-back diode shownin FIG. 5A at different temperatures;

FIG. 6 is an electrical schematic diagram illustrative of the firstembodiment of the subject invention;

FIG. 7 is an electrical equivalent circuit diagram of the embodimentshown in FIG. 6;

FIG. 8 is an electrical schematic diagram further illustrative of theembodiment shown in FIG. 6 and including a pair of switches forimplementing the cancellation of local threshold voltage variations andlow frequency 1/f noise components in the readout signal;

FIG. 9 is a timing diagram illustrative of the switching sequence of acircuit shown in FIG. 8;

FIG. 10 is an electrical schematic diagram illustrative of a secondembodiment of the subject invention;

FIG. 11 is an electrical equivalent circuit diagram of the embodimentshown in FIG. 10;

FIG. 12 is an electrical schematic diagram illustrative of FIG. 10 andincluding a pair of switches for implementing the cancellation of localthreshold voltage variations and low frequency 1/f noise components; and

FIG. 13 is a timing diagram illustrative of the switching sequence ofthe embodiment shown in FIG. 12.

DETAILED DESCRIPTION OF THE INVENTION

Referring now to the drawings wherein like reference numerals refer tolike elements, the sensor shown FIG. 1, overcomes limitations in thermalisolation in conventional bolometers that significantly limits theirsensitivity and make them unsuitable for applications in the 95 GHz(mm-wave) and Terahertz bands, and prevents them from achievingtheoretical performance in the LWIR band. Specifically, calculations andmeasurements have revealed that conventional bolometers areinsufficiently sensitive in the mm band by at least 10×; and unable toachieve theoretical performance in the LWIR spectral band by about 10×.The root cause for the sensitivity degradation in conventionalbolometers is identified below together with the USSS approach forovercoming these limitations in the millimeter, Terahertz & LWIRspectrums.

FIG. 1 discloses a cross section of an Ultra Sensitive Silicon Sensor(USSS) pixel 10 in accordance with the above-referenced related artwhich is comprised of an antenna 12, a detector stage 14, anintermediate stage 16, and a heat bath stage 18 all formed of a siliconand being interconnected by electrical and thermal links G_(2A), G_(2B),G_(3A) and G_(3B). The antenna 12 defines and limits the spectralresponse of the detector stage 14.

Conventional bolometers generally do not use an antenna feed to thedetector nor do they utilize an intermediate stage as shown in FIG. 1.Instead, the detector 14 is directly connected to the substrate (or heatbath) 18 through two thermal links combining G₂ and G₃, that aredesigned to have minimum thermal conductance. Diagrammatically, thiscorresponds to FIG. 1 where the intermediate stage 14 is removed andThermal links G_(2A) is combined with G_(2B) to form a single thermallink G₂; and similarly G_(3A) is combined with G_(3B) to form a singlethermal link G₃.

Thus the detector 14 in conventional bolometers is thermally loaded bylinkages G₂ combined with G₃. Even though G₂ and G₃ are designed to havea poor thermal conductivity (smaller than 1×10⁻⁷ W/K) they are much moreconductive than the thermal conductivity between the scene, not shown,and detector 14; about 10⁻⁹ W/K for LWIR and about 10⁻¹¹ W/K at 95 GHz.The small thermal conductance between the detector 14 and the sceneresults in a tremendous signal attenuation of about 50× at LWIR and5000× in the 95 GHz band. Unfortunately the noise is not attenuated andthis results in very poor sensitivity of about 200 K in the 95 GHz bandand less than the theoretically possible of 1 mK in the LWIR band.

In the Ultra Sensitive Silicon sensor (USSS) 10 as shown in FIG. 1, theuse of an intermediate stage 16 circumvents the thermal loading problemby reducing thermal loading to theoretically limited levels and therebyoffers greatly improved performance. Minimizing thermal loading isautomatically achieved by zeroing the temperature difference between theintermediate stage 16 and the detector stage 14. Zeroing the temperaturedifference between stages 14 and 16 minimizes the thermal loading on thedetector 14 to approach the theoretical radiative limit and thisrepresents greater than a 100 fold reduction of thermal loading overconventional approaches. This “zeroing” (or minimizing the temperaturedifference between the detector and intermediate stages) is implementedwith two silicon diode temperature sensors 20 and 22, such as shown inFIG. 5A, one inside the detector stage 14 and the second collocated withthe amplifier (doubling as the heater) inside the intermediate stage 16.Differences in temperature between the two silicon diode sensors 20 and22 are amplified and the heat generated thereby zeroes the temperaturedifference between the intermediate and detector stages 16 and 14.Cooling from the thermal bath 18 (always below the lowest scenetemperature) combined with the heat output of the amplifier provides forraising and lowering the intermediate stage temperature.

For minimum thermal loading the antenna is ac coupled to the detectorstage 14. In this approach it is significant that no power is dissipatedin the detector 14 by its silicon temperature sensing diode since itoperates like a thermocouple. Such operation negates the need forconventional pulsed readout to provide the minimum noise bandwidth andmaximum sensitivity. Additionally, this monolithic silicon approach willresult in systems orders of magnitude lower in size, weight, and costrelative to conventional RF approaches.

With electro-thermal feedback, the combined conductivities of G_(1A) andG_(2A) (FIG. 1) can be made to approach the radiative limit. The basicconcept of electro-thermal feedback is illustrated in FIG. 2, where itcan be shown that the effective conductance of a thermal link withconductance G₂ can be made to approach zero. Electro-thermal feedback inFIG. 2 employs a thermal amplifier 24 with thermal gain A_(T). Analogousto an electrical amplifier that amplifies voltage, the thermal amplifier24 amplifies temperature. Hence the thermal amplifiers output (T_(IN))and input (T_(D)) temperatures depend on the amplifier's gain A_(T), andT_(IN)=A_(T)T_(D). The thermal loading on the amplifier's input node 26by G₂ depends on the thermal conductivity of G₂ and the thermalamplifier's gain A_(T). The loading on the input node depends on thethermal current Q_(H) flowing through G₂, and this is given as:δQ _(H) =G ₂ [δT _(D) −δT _(IN) ]=G ₂[1−A _(T) ]δT _(D) G _(EFF) =G₂[1−A _(T])  (1)

Where, δQ_(H) is the net thermal current across G₂. Thus the effectiveloading on T_(D) by G₂ depends on the thermal amplifier's gain andresults in an effective conductance, G_(EFF). The thermal amplifier'sgain is determined to minimize the thermal load at the input node 26, attemperature T_(D). This minimization is achieved by adjusting thethermal amplifier's gain to unity. With a unity thermal gain theeffective conductance of G₂ (G_(EFF)) go to zero. The means of makingthe effective conductance of G₂ approach zero is what is needed tominimize thermal attenuation inside a bolometer and thereby maximize thesensitivity. Such an implementation is described next.

Referring now to FIG. 3, electro-thermal feedback is incorporated intoeach pixel 10 of a pixel array, for example, by including anintermediate temperature stage 16 whose temperature is controlled by athermal amplifier 28 described hereafter. FIG. 3 shows the structure ofa three-tier USSS pixel 10 receiving radiant energy via an antenna 12. Adetector stage 14 is attached to the intermediate temperature stage 16and the intermediate stage is attached to a heat bath 18. In aconventional bolometer 10, the detector element 14 would be directlyconnected to a substrate, here labeled as a thermal bath 18, through asingle bridge leg, that can be represented as the sum of bridge legsG_(2A) and G_(2B). The bride legs would be used for electrical accessand readout. The detector stage 14, of the present invention, includes asilicon diode 20 (FIG. 5A) for temperature sensing of the detectorstage's temperature. Two thermal links G_(2A) and G_(2B) connect thedetector stage 14 to the intermediate stage 16. These links provide formechanical support and electrical readout of the detector stage'stemperature. A second silicon diode temperature sensor 22 and a voltageamplifier 28 with gain G>>1 are built into the intermediate stage 16.Four thermal isolation bridges G_(3A), G_(3B) and G_(3C), G_(3D), two ofwhich G_(3A) and G_(3B) are shown, provide mechanical and electricallinkage between the intermediate stage 16 and the heat bath (outsideworld) 18. Line G_(3B) provides B+ to the amplifier 28, and the othertwo lines G_(3A) and G_(3C) (not shown) provide a constant currentI_(H), Line G_(3D) (not shown) is used for removing Correlated NoiseCancellation (CNC) including removal of dc threshold offsets and 1/fnoise components, to be described, once every pixel integration time.The lines G_(3A), G_(3B), G_(3C) and G_(3D) are also used as thermalconductance links between the intermediate stage 16 and the heat bathstage 18.

The USSS approach as shown in FIG. 3 achieves ideal thermal isolationwith electro-thermal feedback. The electro-thermal feedback ismechanized by varying the intermediate stage's 16 temperature T_(IN) inconcert with changes in the detector stage's temperature T_(D). Thepurpose of the thermal amplifier 28 is to equalize the intermediatestage's temperature T_(IN) with the detector stages temperature,monitored by temperature sensor element T_(D). This requires raising andlowering the intermediate stage's temperature T_(IN). This is achievedby combining the heat from the thermal amplifier 28 with cooling fromthe heat bath 18 through conductances G_(3A) and G_(3B), G_(3C), andG_(3D). The intermediate stage's temperature T_(IN) is raised or loweredby adjusting the heat output of the thermal amplifier 28 in combinationwith cooling from the heat bath 18. The heat bath 18 determines theminimum equalization temperature and heater power determines the maximumequalization temperature.

The temperature difference between the intermediate stage 16 and thedetector stage 14 controls the thermal amplifier's heat output. The twoback-to-back connected silicon temperature-sensing diodes 20 and 22shown in FIG. 5A provide a voltage signal proportional to thetemperature difference between the detector stage 14 receiving radiationfrom an antenna element 12 (FIG. 3), and the intermediate stage 16.

The voltage difference signal α(T_(D)−T_(IN)), where α≅−1.5 mV/K, isamplified by gain G>>1 to provide a voltage signal V_(OUT). Since theamplifier 28 operates at a constant current I_(H), the power consumed bythe amplifier, and delivered to heat to the intermediate stage 16, isproportional to the voltage V_(OUT). Specifically, amplifier's outputpower is Q_(H)=I_(H)[Gα(T_(D)−T_(IN))]=A[T_(D)−T_(IN)], where A=I_(H)Gα.Since the temperature of the intermediate stage 16 and detector stage 14are made substantially equal, the output voltage signal V_(OUT) isproportional to changes in the scene temperature δT_(S).

The efficacy of the electro-thermal feedback is determined with energybalance equations at the detector stage 14 and the intermediate stages16. The absorber element of the detector stage 14, with a heat capacityC_(D) receives radiative energy Q_(R) via antenna 12 from a remotescene, not shown, and radiation shields Q_(S1), also not shown. Thedetector stage 14 also radiates energy Q_(D1) through a 4π angle andcontacts the intermediate stage 16 through two thermal linksG_(2A)+G_(2B)=G₂. The heat capacity of intermediate stage 16 is C_(IN),and it is connected to the heat bath 18 through thermal links G_(3A) andG_(3B). The intermediate stage receives radiation Q_(S2) from theradiation shields, not shown, and radiates energy Q_(D2). The energybalance equation at the detector stage is given by: $\begin{matrix}{{\left( {Q_{R} - Q_{D1}} \right) + \left( {Q_{AS} - Q_{AE}} \right) + {\int_{T_{D}}^{T_{IN}}{{G_{2}(T)}\quad{\mathbb{d}T}}}} = {\int_{T_{D}}^{T_{D} + {\delta\quad T_{D}}}{j\quad\omega\quad{C_{D}(T)}\quad{\mathbb{d}T}}}} & (2)\end{matrix}$

In Equation 2, Q_(R) (Q_(D1)) is the radiation directly received(emitted) by the detector stage 14; Q_(AS) (Q_(AE)) is the radiationdirectly received (emitted) by the antenna 12 and channeled into(removed from) the detector 14, and C_(D) is the heat capacity of thedetector stage 14. Similarly, the energy balance equation at theintermediate stage is given by: $\begin{matrix}{{{- Q_{D2}} + Q_{S2} + Q_{H} + {\int_{T_{IN}}^{T_{HB}}{{G_{3}(T)}\quad{\mathbb{d}T}}} + {- {\int_{T_{D}}^{T_{IN}}{{G_{2}(T)}\quad{\mathbb{d}T}}}}} = {\int_{T_{IN}}^{T_{IN} + {\delta\quad T_{IN}}}{j\quad\omega\quad{C_{IN}(T)}\quad{\mathbb{d}T}}}} & (3)\end{matrix}$

In Equation 3, Q_(D2) (Q_(S2)) is the radiation emitted (received)directly by the intermediate stage 16, Q_(H) is the heat delivered bythe electro-thermal feedback voltage amplifier 28 to the intermediatestage 16, and C_(IN) is the heat capacity of the intermediate stage 16.Taking the differentials of Equations 2 and 3, two new linearizedequations are obtained, namely:[G _(R) +G _(AS) ]δT _(S) −[G _(D1) +G ₂ +jωC _(D) ]δT _(D) +[G ₂ ]δT_(IN)=0  (4)and,−[G _(D2) +G ₂ +G ₃ +jωC _(IN) ]δT _(IN) +G ₂ δT _(D) +δQ _(H)=0  (5)

Terms G_(R), G_(D1), G_(AS), G_(D2), G_(S2), and δQ_(H) are obtained bytaking the temperature differentials of Q_(R), Q_(D1), Q_(AS), Q_(D2),Q_(S2), and Q_(H), respectively. The antenna 12, which in actuality is amicroantenna, is held at the heat bath temperature, and its temperaturedifferential is δQ_(AE)=G_(AE)δT_(HB)=0. In addition, the intermediatestage 16 is shielded by the heat bath 18, hence the differential of theenergy it receives directly is δQ_(S2)=G_(S2)δT_(HB)=0.

Temperature tracking by the intermediate stage 16 of the detectorstage's temperature 14 is revealed by Equation 5 when the expressionδQ_(H)=AδT_(D)−AδT_(IN) is included the relationship between thedetector stage and intermediate stage temperatures is given as:$\begin{matrix}{{\delta\quad T_{IN}} = {\frac{\left( {A + G_{2}} \right)}{\left( {G_{2} + G_{D2} + G_{3} + A + {j\quad\omega\quad C_{IN}}} \right)}\delta\quad T_{D}}} & (6)\end{matrix}$

Incorporating a large electro-thermal feedback the coefficient A in thedesign, makes A large relative to all the other conductive terms inEquation 6, i.e., A>>{G₂, G₃, G_(D2)}, thereby achieving a conditionwhere the differential temperature changes in the detector stage 14 areessentially equal to intermediate stage 16 changes. This condition isequivalent to no AC thermal current through G₂, and its effectivethermal conductivity approaches zero.

The Ultra Sensitive Silicon Sensor's (USSS) pixel readout circuitsdisclosed herein are critical to achieving electro-thermal feedback thatleads to high performance. The readout circuits employ the minimumnumber of components thereby facilitating manufacturability, a smallfoot print (<50 μm×50 μm), and low power consumption (<30 μW).Additionally, the readout circuits have several thermal and electricalrequirements. The thermal requirements include incorporation of thereadout circuit into the electro-thermal feedback loop for temperatureequalization between the detector and intermediate stages. Theelectrical requirements include low noise, high temperature sensitivityand large voltage gain, leading to a large electro-thermal coefficientA.

Operation of the electro-thermal loop requires temperature sensingelements and for maximum simplicity and lowest power consumption,silicon p/n junction thermocouples are employed and they will bedescribed first. Two different circuit embodiments for implementing theelectro-thermal feedback are described. One embodiment utilizes aninverting amplifier and the other a non-inverting amplifier. Theseembodiments, moreover, incorporate means for improving theirsensitivity. The sensitivity improvement stems from incorporating intotheir readout circuits means to cancel local MOS threshold voltagevariations and suppression of low frequency 1/f noise. The MOS thresholdoffsets and 1/f noise canceling technique are referred to as CorrelatedNoise Cancellation (CNC). With CNC sensitivity degradations that wouldbe produced by MOS threshold variations and 1/f noise are nowcircumvented.

Temperature sensing and compensation are built into each USSS readoutcircuit. The temperature sensing is used to determine the temperaturedifference between the detector stage 14 and intermediate stage 16 andprovides an output that controls the electro-thermal feedback loop thatzeroes this temperature difference between these stages. Effects ofresponse offsets in the temperature sensing diodes 20 and 22 (FIG. 5A)are calculated and techniques for their cancellation are provided.Response offsets between the detector and intermediate stage temperaturesensing diodes 20 and 22, if not removed, would corrupt the operation ofthe electro-thermal feedback loop. These issues are addressed startingby describing the temperature sensing diodes 20 and 22 used fordetecting the temperature difference between the detector stage 14 andintermediate stage 16.

The temperature sensing diodes 20 and 22 of the present invention areselected so as to satisfy three major requirements: first, highdifferential temperature sensitivity; second, being made oftechnologically mature silicon material, and third, they consume zeropower and thereby minimize 1/f noise and readout errors due to selfheating. These requirements are satisfied with two silicon p/n junctiondiodes 20 and 22 connected back to back, as shown in FIG. 5A. Silicondiodes 20 and 22 sense the detector's and intermediate's stagetemperatures, respectively, and provide a voltage signal proportional tothe temperature difference between the detector stage 14 andintermediate stage 16. The operation of a silicon diode is well known;however, a description is provided below.

Referring now to FIG. 4, it is well known that in a semiconductor theband gap, E_(BG), and the Fermi level change with temperature. At zerocurrent flow, the Fermi levels of the n-type region lines up with theFermi level of the p-type diode region. This is shown in FIG. 4 where atzero current flow the n-type Fermi level E_(FN) is lined up with thep-type Fermi level E_(FP). This alignment results in a potential offsetΔΦ_(D)(T_(D)) between the conduction bands across the junction. Thispotential offset depends on the band gap and the Fermi levels E_(FN),and E_(FP). Since the band gap and the Fermi levels are temperaturedependent, it follows that the potential offset ΔΦ_(D)(T_(D)) is alsotemperature dependent. The differential temperature sensor in accordancewith the subject invention is based on this phenomenon.

In FIG. 4, the band diagram shown is of a single silicon p/n junction.The intrinsic Fermi level, E_(FI) is shown in the respective n-type andp-type diode segments. The extrinsic Fermi levels line up at zerocurrent flow. V_(N) (V_(P)) is the potential difference between theconduction (valence) band E_(FN) (E_(FP)) and the extrinsic Fermi level.The Silicon band gap is labeled as E_(BG). The potential difference isproduced by the space charge formed at the p/n junction. Positive spacecharge is formed at the N-side and negative space charge is formed atthe P-side. The positive and negative space charge at the diode's p/njunction thus acts as a temperature dependent voltage source.

The value and temperature dependence of a p/n junction's potentialoffset ΔΦ_(D)(T_(D)) is calculated using a well known procedure and canbe expressed as:qΔΦ _(D)(T _(D))=E _(BG) −[qV _(N) +qV _(p)]  (7)

The right side of Equation 7 is a function of temperature, and thetemperature dependence for the Silicon band gap is: $\begin{matrix}{E_{BG} = {{kT}_{D}\quad{{Ln}\left( \frac{N_{C}N_{V}}{n_{i}^{2}} \right)}}} & (8)\end{matrix}$Where k is Boltzmann's constant and T is the temperature in degreesKelvin. The expressions for N_(V) and N_(C) will drop out when all theterms are summed in Equation 7. The explicit temperature dependantexpression for V_(N) and V_(P) can be written as: $\begin{matrix}\begin{matrix}{V_{N} = {{kT}_{D}\quad{{Ln}\left( \frac{N_{C}}{n_{no}} \right)}}} \\{V_{P} = {{kT}_{D}\quad{{Ln}\left( \frac{N_{V}}{p_{po}} \right)}}}\end{matrix} & (9)\end{matrix}$where, p_(po) and n_(no) are the equilibrium concentration of electronsand holes, respectively. Substituting Equations 8 and 9 into Equation 7and simplifying, obtained is: $\begin{matrix}{{q\quad\Delta\quad{\Phi_{D}\left( T_{D} \right)}} = {{{kT}_{D}\quad{{Ln}\left( \frac{n_{no}p_{po}}{n_{i}^{2}} \right)}} \cong {{kT}_{D}\quad{{Ln}\left( \frac{N_{A}N_{D}}{n_{i}^{2}} \right)}}}} & (10)\end{matrix}$

The approximations in Equation (10) assume that the equilibrium electronconcentration is equal to the donor doping level, n_(no)≅N_(D), and theequilibrium hole concentration is equal to the acceptor concentrationp_(po)≅N_(A). The explicit expression for (n_(i))² is also obtained fromSze and for Silicon is expressed as: $\begin{matrix}{n_{i}^{2} = \left\lbrack {4.9 \times 10^{15}\left( \frac{m_{de}m_{dh}}{m_{o}^{2}} \right)^{3/4}T^{3/2}\quad{\exp\left( \frac{- E_{BG}}{2{kT}_{D}} \right)}} \right\rbrack^{2}} & (11)\end{matrix}$

The effective hole m_(dh) and electron m_(de), masses are readilyobtained from a handbook in terms of the rest mass m_(o). Performing allthese substitutions, the ration of the effective masses in Equation 10is (m_(de)m_(dh)/m_(o) ²)^(3/4)=0.62849. An explicit expression for theSilicon bandgap as a function of temperature can be stated as:$\begin{matrix}{{E_{BG}(V)} = {q\left( {1.170 - \frac{4.73 \times 10^{- 4}T_{D}^{2}}{636 + T_{D}}} \right)}} & (12)\end{matrix}$

Substituting Equations 10 and 11 into Equation 9, and after somesimplifications, obtained is: $\begin{matrix}{{\Delta\quad{\Phi_{D}\left( T_{D} \right)}} = {{\frac{{kT}_{D}}{q}\quad{{Ln}\left( \frac{N_{A}N_{D}}{9.49 \times 10^{30}T_{D}^{3}} \right)}} + 1.170 - \frac{4.73 \times 10^{- 4}T_{D}^{2}}{636 + T_{D}}}} & (13)\end{matrix}$

Equation 13 represents the temperature dependence of the potentialoffset between the conduction and valance bands across a diode. Thetemperature dependence of ΔΦ_(D)(T_(D)) is readily computed by takingthe derivative of Equation 13 and can be stated as, $\begin{matrix}{\frac{{\partial\Delta}\quad{\Phi_{D}\left( T_{D} \right)}}{\partial T_{D}} = {{\frac{k}{q}\quad{{Ln}\left\lbrack \frac{N_{A}N_{D}}{9.49 \times 10^{30}T_{D}^{3}} \right\rbrack}} - \frac{3k}{q} - {4.73 \times {10^{- 4}\left\lbrack {1 - \left( \frac{636}{636 + T_{D}} \right)^{2}} \right\rbrack}}}} & (14)\end{matrix}$

Evaluating Equation 14, assuming N_(A)≅N_(D)≅10¹⁷ dopants/cm³ andT_(D)=300 K, the value for the differential temperature signal∂Φ_(D)(T_(D))/∂T_(D)=−1.3888 mV/K. This represents at least a 20 foldincrease in temperature sensitivity than metallic thermocouples. Thenegative sign indicates that as temperature T_(D) increases the diode'spotential output signal decreases.

Referring now to FIGS. 5A and 5B, connecting two diodes 20 and 22 asshown in FIG. 5A in series provides a signal directly proportional tothe temperature difference between the detector and intermediate stages.FIG. 5B is illustrative of the band diagram of two diodes 20 and 22connected in series and the potential produced by having each at adifferent temperature. The diodes 20 and 22 are thermally isolated fromeach other with diode 20 (D_(D)) being at the detector's temperatureT_(D), and diode 22 (D_(IN)) being at the intermediate stage'stemperature T_(IN). The total potential drop produced across the twodiodes 20 and 22 is:ΔΦ(T _(D) ,T _(IN))=ΔΦ_(D)(T _(D))−ΔΦ_(IN)(T _(IN))  (15)Where expressions for ΔΦ_(D)(T_(D)) and ΔΦ_(IN)(T_(IN)) are given byEquation 13. If the diodes 20 and 22 are at the same temperature(T_(D)=T_(IN)), there is no potential offset produced thereby, and asexpected ΔΦ(T_(D),T_(IN))=0. The temperature sensitivity computed withEquation 14 is consistent with the values used in analyzing theperformance of the electro-thermal feedback and the USSS readout circuitof the subject invention. Temperature compensation in the readoutcircuit is considered next.

In FIG. 5A, two Silicon diodes 20 and 22, at temperatures T_(D) andT_(IN), respectively, are connected back to back to provide a potentialsignal dependent on their temperature difference. The temperaturedependence of ΔΦ(ΔT_(D),T_(IN)) is used to provide a differential signalrelated to temperatures T_(D) and T_(IN).

Temperature compensation inside the readout circuit of the subjectinvention is needed to insure that only the temperature differencebetween the sensing silicon p/n junction diodes effect theelectro-thermal feedback loop. The USSS readout circuit needs to takeinto account the temperature dependence of the transistors used toimplement the electro-thermal feedback loop. The temperature dependenceof the threshold voltage is computed with an analysis that can be foundin many semiconductor textbooks. The threshold voltage of a MOS (metaloxide silicon) field effect transistor (MOSFET) is known to vary withtemperature, and this variation with temperature can be stated as:V _(T)=ΔΦ_(D)(T _(IN))+√{square root over (2ε_(S) qN _(D)[ΔΦ_(D)(T_(IN))])}/C _(i)  (16)where ε_(s) is the dielectric constant of a MOSFET substrate, N_(D) isthe donor concentration in the substrate, and C_(i) is the MOSFET gatecapacitance per unit area. Equation (16) includes the potential shiftΔΦ_(D)(T_(D)) that the potential applied to the MOS gate needs to affectso that the FET channel will be biased into weak inversion and therebystart the flow of current in the channel. The potential shift moves thechannel from flat band of the N type substrate to weak inversion whichcorresponds to the potential of p-type silicon. Accordingly, in Equation(16), the notation of 2ψ_(B) has been replaced by ΔΦ_(D)(T_(D)). Itshould be noted that ΔΦ_(D)(T_(D)) also directly represents the diode'sthermal EMF that will be detailed later. Thus the variation in the MOSthreshold voltage with temperature is readily computed by taking thederivative of Equation (16) and after some rearrangement, the expressionobtained is: $\begin{matrix}{\frac{\partial V_{T}}{\partial T_{IN}} = {\frac{{\partial\Delta}\quad{\Phi_{D}\left( T_{IN} \right)}}{\partial T_{IN}}\left\lbrack {1 + {\frac{1}{C_{i}}\sqrt{\frac{ɛ_{S}\quad q\quad N_{D}}{2\quad\Delta\quad{\Phi_{D}\left( T_{IN} \right)}}}}} \right\rbrack}} & (17)\end{matrix}$

In calculating Equation (17) T_(D) has been replaced with T_(IN) toreflect the fact that the MOSFET is at the intermediate temperatureT_(IN) and not at the detector temperature T_(D). It is evident that thedifferential temperature dependence of the threshold voltage is largerthan the differential temperature dependence of the detector's p/ndiode, but has the same sign. The increase in the relative value of thethreshold voltage's differential temperature dependence is given by thesecond term in the brackets of Equation (17). This term is evaluated bysubstituting N_(D)≅10¹⁶, C_(i)≅d_(OX)/ε_(OX) with d_(OX)≅10⁻⁶ cm andε_(OX)≅3.9_(εO), ε_(Si)=11.9ε_(O) and the potential differenceΔΦ_(D)(T_(D))≅0.8V. Substituting all these values into Equation (17) thedifferential temperature dependence of the threshold voltage can bestated as: $\begin{matrix}{\frac{\partial V_{T}}{\partial T_{IN}} = {\frac{{\partial\Delta}\quad{\Phi_{D}\left( T_{IN} \right)}}{\partial T_{IN}}\left\lbrack {1 + 0.1189} \right\rbrack}} & (18)\end{matrix}$

Thus, an n/p diode and MOS transistor have temperature dependenceswithin 12%. It should be evident that compensation of the temperaturedependence of the MOS threshold voltage is important and the circuitneeds to be symmetric to cancel the temperature dependence of thereadout circuit's transistors. This temperature compensation is builtinto the pixel readout circuits using inverting and non-invertingamplifiers as will be explained below.

Additionally, the readout circuits of the present invention have beendesigned to accept signals from the two diode temperature sensors 20 and22 with very high impedance. The diode temperature sensor's output drivecapability is inversely related to the diode temperature sensitivity.The differential temperature sensitivity of the series back-to-backconnected diodes 20 and 22 (FIG. 5A) is a function of the donor (N_(D))and acceptor (N_(A)) concentrations is given by Equation 14. Improvedsensitivity can be further obtained with smaller donor and acceptorconcentrations. However, with lower donor and acceptor concentrations,the back to back diodes' impedance is increased and the drive capabilityreduced. Hence the pixel readout circuits are designed to have a highimpedance to minimize drive requirements by the p/n diodes.

The voltage signal produced by the back-to-back diodes 20 and 22originates from the space charge formed at the diode's junction, whichchange with temperature. Thus the impedance of this circuit correspondsto that of two charged capacitors connected in series. The charge acrosseach capacitor is produced at the diodes' 20 and 22 p/n junctions andchanges with temperature. Clearly, the impedance of the two seriescapacitances is very high and consequently has very limited drivecapability. With such high impedance, the only circuit the twoback-to-back diodes can most readily drive is the gate of a MOSFET. Tominimize attenuation, the MOS gate capacitance should be much smallerthan each of the two diode p/n junction capacitances. For the donor(N_(D)) and acceptor (N_(A)) concentration of 10¹⁷/cm³, the junctioncapacitance for a 5 μm disk is about 6 fF. This very small capacitancedemands an amplifier with a very low effective input capacitance. Fieldeffect transistors (FETs) are excellent candidates and are used in thepresent invention in two different circuit types to amplify the signalfrom the two back to back temperature sensing diodes. The diodecapacitance can be increased by increasing the donor and/or acceptorconcentration. However, this will make things worse. The space chargesignal increases logarithmically with N_(D) and N_(A), while thecapacitance increases faster, as the square root of theseconcentrations. Hence the voltage signal would decrease faster than thereduction in loading leading to a poorer performance. The selection of,approximately, N_(D) and N_(A) of about 10¹⁷/cm³ has proved to be a goodcompromise

Referring now to FIG. 6, a first circuit 32 is shown for implementingthe electro-thermal loop is an inverting symmetrical FET amplifier. TheFET inverting amplifier of FIG. 6 includes electro-thermal feedback aswell as provisions for threshold and 1/f noise cancellation elements.For clarity, the correlate noise cancellation (CNC) switches forremoving the threshold offsets and low frequency 1/f noise are omittedfrom FIG. 6, but are shown, for example, in FIG. 8. The invertingamplifier includes two temperature sensors 20 and 22 driving the FETgate of transistor T₁. The detector stage's temperature sensor is adiode 20 (T_(D)) and the intermediate stage's temperature sensor is witha second diode 22 (T_(IN)). The temperature sensing diodes have the sametemperature characteristics.

The electro-feedback circuit of this invention incorporates provisionsfor temperature sensing and heating to equalize the temperatures of theintermediate stage 16 with the temperature of the detector stage 14. Acascode stage 34, implemented by a FET transistor T₃ connected to thedrain of FET T₁, is added to minimize capacitive loading on the twodiode temperature sensors 20 and 22. As noted above, the CNC switchingcircuit elements are left out for clarity. The temperature dependence ofthe amplifier 32 is cancelled by utilizing a symmetrical design. Thetemperature dependent threshold voltage of the FET T₁ is cancelled withFET T₂. T₁ and the T₂ operate at the same current levels to achievetemperature cancellation, and threshold cancellation, to first order.This cancellation is important for the temperature dependence of thethreshold voltage is comparable to the temperature dependence of thetemperature sensing p/n junction silicon diodes 20 and 22.

Eliminating the inverting amplifier's 32 temperature dependence isimportant for the operation of the electro-thermal feedback loop.Additionally, the effectiveness of the electro-thermal feedback loopdepends on the T₁/T₃ amplifier's voltage gain. T₃ has been included inthe circuit in FIG. 6 to minimize the Miller capacitance at the gateinput of the T₁ and thus maximize the voltage gain. This is furtherfacilitated by utilizing high impedance current generators. Thus,amplification of the input signal produced from the two back-to-backdiode thermocouples 20 and 22 depends on two factors. First, attenuationof back-to-back diode thermocouples voltage signal due to loading by theamplifiers input impedance. Second, this attenuation will be offset bythe voltage gain that depends on the transconductance of T₁/T₃ times theimpedance at the output node 36 V(OUT).

Analysis of this inverting circuit is done in the high frequency limitto determine effects of parasitic loading. The output signal due to thetemperature difference between the detector 14 and intermediate stage 16diodes is computed using superposition, and the aid of an equivalentcircuit as shown in FIG. 7.

Referring now to the equivalent circuit FIG. 7, the inverting amplifier,composed of T₁/T₃ and the current generator load, has been formulated tohave large voltage gain G. The output impedance of T₁ is very high and asecond stage T₃ is used to increase this impedance and minimizecapacitive loading when driving the output bus 38, and increase thevoltage gain. The threshold voltage (including 1/f noise components) ofT₁ is represented as V_(IN1). Relative to the diode thermocouples, thecapacitance of T₂ is very small and its threshold voltage (including 1/fnoise components) is represented as a voltage V_(IN2). There are severalparasitic capacitances included in this analysis. Capacitance C_(P) isthe parasitic capacitance between the substrate and the P+ regions ofthe temperature sensing diodes 20 and 22. Capacitance C_(PP) is theparasitic capacitance between the detector's N+ thermocouple region ofdiode 20 and the substrate. Capacitance C_(GD) is the parasiticcapacitance between the gate of T₁ and the drain. Capacitance C_(GS) isthe parasitic capacitance between the gate of T₁ and the source. Becausethe thermocouple sensing diodes operate as thermocouples with zeroequilibrium current, they are best represented in the analysis ascapacitors with temperature dependent charge. This is a high frequencyanalysis and represents the worst case for impedance loading. Again, forclarity, CNC switches are omitted in this analysis.

The analysis derives the output voltage V(OUT) as a function of changesin the voltage across the two thermocouple diodes 20 and 22.Superposition is used to derive the transfer function between eachthermocouple 20 and 23 and the output V(OUT). The output voltage fromthe detector stage diode thermocouple diode 20 is derived as follows.The three-charge currents δq₁, δq₂, and δq₃, are produced withtemperature changes in the two thermocouples temperature sensing diodes20 and 22. Mesh equations for each one of these three charge currentsprovide expressions that are used to compute the resulting signalapplied at the gate of the T₁. The three equilibrium mesh equations canbe expressed as:V _(P) +V _(IN) +V _(IN1) −V _(G)=0  (19)V _(P) +V _(D) −V _(PP)=0  (20)−V _(IN2) +V _(S/H) −V _(PP)=0  (21)Rewriting Equations 19, 20 and 21 in terms of charges on capacitorsthree equations are obtained and are given as: $\begin{matrix}{{\frac{Q_{P}}{C_{P}} + \frac{Q_{IN}}{C_{IN}} + V_{IN1} - V_{G}} = 0} & (22) \\{{\frac{Q_{P}}{C_{P}} + \frac{Q_{D}}{C_{D}} - \frac{Q_{PP}}{C_{PP}}} = 0} & (23) \\{{{- V_{IN2}} + \frac{Q_{S/H}}{C_{S/H}} - \frac{Q_{PP}}{C_{PP}}} = 0} & (24)\end{matrix}$

A change in charge on the detector's thermocouple diode 20 by ΔQ_(D)will produce a transient flow of three charge currents and they willresult in a voltage change on the gate of T₁. The three Equationsgoverning these changes are: $\begin{matrix}{{\frac{Q_{P} - {\delta\quad q_{1}} - {\delta\quad q_{2}}}{C_{P}} + \frac{Q_{IN} - {\delta\quad q_{1}}}{C_{IN}} + V_{IN1} - V_{G} - {\delta\quad V_{G}}} = 0} & (25) \\{{\frac{Q_{P} - {\delta\quad q_{1}} - {\delta\quad q_{2}}}{C_{P}} + \frac{Q_{D} + {\Delta\quad Q_{D}} - {\delta\quad q_{2}}}{C_{D}} - \frac{Q_{PP} + {\delta\quad q_{2}} + {\delta\quad q_{3}}}{C_{PP}}} = 0} & (26) \\{{{- V_{IN2}} + \frac{Q_{S/H} - {\delta\quad q_{3}}}{C_{S/H}} - \frac{Q_{PP} + {\delta\quad q_{2}} + {\delta\quad q_{3}}}{C_{PP}}} = 0} & (27)\end{matrix}$The voltage on the gate of T₁ changes as the transient current δq₁changes the charge on the gate capacitance C_(GS) and C_(GD) and thisresults in: $\begin{matrix}{{\delta\quad V_{G}} = \left( \frac{\delta\quad q_{1}}{C_{GS} + C_{GD}} \right)} & (28)\end{matrix}$Using Equation 28 to get rid of δV_(G) in Equation 25 and combiningEquations 25, 26, and 27 with Equations 22, 23, and 24, what is obtainedafter grouping of terms are three new equations: $\begin{matrix}{{{\left( {\frac{1}{C_{P}} + \frac{1}{C_{IN}} + \frac{1}{C_{GS} + C_{GD}}} \right)\quad\delta\quad q_{1}} + \frac{\delta\quad q_{2}}{C_{P}}} = 0} & (29) \\{{\frac{\delta\quad q_{1}}{C_{P}} + {\left( {\frac{1}{C_{P}} + \frac{1}{C_{D}} + \frac{1}{C_{PP}}} \right)\quad\delta\quad q_{2}} + \frac{\delta\quad q_{3}}{C_{PP}}} = \frac{\Delta\quad Q_{D}}{C_{D}}} & (30) \\{{\frac{\delta\quad q_{2}}{C_{PP}} + {\left( {\frac{1}{C_{PP}} + \frac{1}{C_{S/H}}} \right)\quad\delta\quad q_{3}}} = 0} & (31)\end{matrix}$

The expression for δq₁ in terms of ΔQ_(D) and the various capacitancesin the equivalent circuit in FIG. 7 is obtained by using Equation 31 toget rid of the variable δq₃ and Equation 29 to get rid of variable δq₂in Equation 30, and then solving for δq₁ in terms of ΔQ_(D), thereresult is: $\begin{matrix}{{\delta\quad q_{1}} = {\frac{{- \Delta}\quad Q_{D}}{C_{D}}\frac{1}{\begin{matrix}{{\left( {\frac{1}{C_{GS} + C_{GD}} + \frac{1}{C_{IN}}} \right)\left( {1 + \frac{C_{P}}{C_{D}} + \frac{C_{P}}{C_{S/H} + C_{PP}}} \right)} +} \\\left( {\frac{1}{C_{D}} + \frac{1}{C_{S/H} + C_{PP}}} \right)\end{matrix}}}} & (32)\end{matrix}$Combining Equation 28 with Equation 32, the change in the FET invertingamplifiers gate voltage due to changes in the detector stage temperatureis obtained which can be expressed as: $\begin{matrix}{{\delta\quad{V_{G}\left( {\Delta\quad T_{D}} \right)}} = {\frac{{- \Delta}\quad Q_{D}}{C_{D}}\frac{(1)}{\begin{matrix}\left\lbrack {1 + {C_{P}/C_{D}} + {C_{P}/\left( {C_{S/H} + C_{PP}} \right)}} \right\rbrack \\\left\lbrack {1 + {\left( {\frac{1}{C_{IN}} + \frac{{1/C_{D}} + {1/\left( {C_{S/H} + C_{PP}} \right)}}{1 + {C_{P}/C_{D}} + {C_{P}/\left( {C_{S/H} + C_{PP}} \right)}}} \right)\left( {C_{GS} + C_{GD}} \right)}} \right\rbrack\end{matrix}}}} & (33)\end{matrix}$

The negative sign in front of Equation 33 indicates that the voltagepolarity assigned to δV_(G) in response to the change ΔQ_(D) on thedetector thermocouple is in the wrong direction. However, it should benoted if the parasitic capacitors C_(PP) and C_(P) are made very small,the coupling would approach unity between the detector's diodethermocouple 20 and the gate of T₁. The gate capacitance of the T₁,C_(GS)+C_(GD), should be made as small as possible to maximize response.A smaller FET gate capacitance is possible by minimizing the T₁'schannel concentration.

The output voltage V(OUT) will depend on the voltage gain of theinverting amplifier T₁. The gain of the T₁ is approximated as a productof the transconductance times the output impedance. At low operatingcurrent (about one microamp), the transconductance is almost geometryindependent and depends only on the drain current. The output impedanceis determined by the output impedance at T₃ and the impedance of thecurrent generator I_(H). With proper care, both of these can be made tobe very large, and a voltage gain of several tens of thousand betweenthe gate and the drain can be achieved. Hence, the gate voltage on T₁given by Equation 33 will be amplified be more than ten thousand times.

The transfer function between the gate voltage of T₁ and theintermediate stage thermocouple diode 22 is derived next. Calculation ofthe effect of changes in the intermediate stage thermocouple 22 is madethe same way as for the detector stage thermocouple diode 20. Transientchanges in the three currents δq₁, δq₂, and δq₃, will occur with changesin the temperature of the intermediate stage diode thermocouple 22. Meshequations for each one of these three transient changes in the chargecurrents δq₁, δq₂, and δq₃ provide expressions that can be used toderive the resulting voltage signal applied at the gate of the T₁. Thethree equilibrium mesh equations have been previously obtained and arethe same as Equations 22, 23, and 24. Modifying Equations 29 and 30 toinclude ΔQ_(D)=0, and instead have a change in ΔQ_(IN), and a set ofthree Equations are obtained which can be expressed as: $\begin{matrix}{{\frac{Q_{P} - {\delta\quad q_{1}} - {\delta\quad q_{2}}}{C_{P}} + \frac{Q_{IN} + {\Delta\quad Q_{IN}} - {\delta\quad q_{1}}}{C_{IN}} + V_{IN1} - V_{G} - {\delta\quad V_{G}}} = 0} & (34) \\{{\frac{Q_{P} - {\delta\quad q_{1}} - {\delta\quad q_{2}}}{C_{P}} + \frac{Q_{D} - {\delta\quad q_{2}}}{C_{D}} - \frac{Q_{PP} + {\delta\quad q_{2}} + {\delta\quad q_{3}}}{C_{PP}}} = 0} & (35) \\{{{- V_{IN2}} + \frac{Q_{S/H} - {\delta\quad q_{3}}}{C_{S/H}} - \frac{Q_{PP} + {\delta\quad q_{2}} + {\delta\quad q_{3}}}{C_{PP}}} = 0} & (36)\end{matrix}$The voltage on the gate of T₁ changes as the current δq₁ changes and hasbeen given before by Equation 28. Using Equation 28 to get rid of δV_(G)in Equation 34 and combining Equations 34, 35, and 36 with Equations 22,23, and 24, after grouping of terms three new equations are obtainedwhich are: $\begin{matrix}{{{\left( {\frac{1}{C_{P}} + \frac{1}{C_{IN}} + \frac{1}{C_{GS} + C_{GD}}} \right)\quad\delta\quad q_{1}} + \frac{\delta\quad q_{2}}{C_{P}}} = \frac{\Delta\quad Q_{IN}}{C_{IN}}} & (37) \\{{\frac{\delta\quad q_{1}}{C_{P}} + {\left( {\frac{1}{C_{P}} + \frac{1}{C_{D}} + \frac{1}{C_{PP}}} \right)\quad\delta\quad q_{2}} + \frac{\delta\quad q_{3}}{C_{PP}}} = 0} & (38) \\{{\frac{\delta\quad q_{2}}{C_{PP}} + {\left( {\frac{1}{C_{PP}} + \frac{1}{C_{S/H}}} \right)\quad\delta\quad q_{3}}} = 0} & (39)\end{matrix}$Comparing Equations 37, 38 and 39 to Equations 29, 30 and 31, thesymmetry can be readily seen. Deriving the expression for δq₁ in termsof ΔQ_(IN) and the various capacitances in the equivalent circuit ofFIG. 7 is obtained by using Equation 39 to get rid of the variable δq₃in Equation 38. Next, the resulting Equation 38 replaces δq₂ in Equation37, and solving for δq₁ in terms of ΔQ_(IN) the result is:$\begin{matrix}{{\delta\quad q_{1}} = {\frac{\Delta\quad Q_{IN}}{C_{IN}}\frac{1}{\frac{1}{C_{GS} + C_{GD}} + \frac{1}{C_{IN}} + \frac{{1/C_{D}} + {1/\left( {C_{S/H} + C_{PP}} \right)}}{1 + {C_{P}/C_{D}} + {C_{P}/\left( {C_{S/H} + C_{PP}} \right)}}}}} & (40)\end{matrix}$Combining Equation 28 with Equation 40, the change in the gate voltageof inverting amplifier T₁ as a function of temperature changes in theintermediate stage is: $\begin{matrix}{{\delta\quad{V_{G}\left( {\Delta\quad T_{IN}} \right)}} = {\frac{\Delta\quad Q_{IN}}{C_{IN}}\frac{1}{1 + {\left\lbrack {\frac{1}{C_{IN}} + \frac{{1/C_{D}} + {1/\left( {C_{S/H} + C_{PP}} \right)}}{1 + {C_{P}/C_{D}} + {C_{P}/\left( {C_{S/H} + C_{PP}} \right)}}} \right\rbrack\left( {C_{GS} + C_{GD}} \right)}}}} & (41)\end{matrix}$

The transfer functions for the detector stage's 14 (Equation 33) andintermediate stage's 16 (Equation 41) diode thermocouples 20 and 22,respectively, are different. For proper operation, the sign differencebetween these transfer functions is correct. Decreasing the temperatureof the detector stage 14 requires automatic cooling of the intermediatestage 16. The transfer function (Equation 33) will produce a negativesignal on the gate of T₁ and V(OUT) will become more positive (closer toground). A more positive V(OUT) will reduce the intermediate stage 16temperature until it converges to the detector stage 14 temperature.Similarly, if the intermediate stage 16 temperature is too high(decreasing the thermocouple charge (ΔQ_(IN)), the transfer function(Equation 41) will cause a smaller voltage on the gate of T₁ and thiswill change V(OUT) to be more positive (or closer to the ground). AsV(OUT) moves closer to ground, the quiescent power consumed by theamplifier 32 decreases causing the intermediate stage 16 to cool towardthe detector stage 14 temperature.

Qualitatively, the frequency analysis has demonstrated that theelectro-thermal feedback loop is working correctly. However, properoperation requires that, besides the sign, the transfer functions givenby Equations 33 and 41 be identical. This is readily achieved byequating the two transfer functions and obtaining the requirements forequality by adjusting the relative values of C_(D) and C_(IN) to be,C _(IN)=[1+C _(P) /C _(D) +C _(P)/(C _(S/H) +C _(PP))]C _(D)  (41)

This relationship between C_(D) and C_(IN) is readily accomplished byproperly scaling the thermocouple diode's parasitic areas. Once the USSSunit cell is laid-out prior to fabrication, the values for C_(P), C_(PP)and C_(S/H) can be computed and the thermocouple diode's parasitic areasadjusted accordingly. Making all these adjustments, the overall transferfunction for the circuit shown in FIG. 6 is: $\begin{matrix}{{V({OUT})} = {\left\lbrack \frac{{\Delta\quad Q_{IN}} - {\Delta\quad Q_{D}}}{C_{IN}} \right\rbrack\quad\frac{g_{M}Z_{OUT}}{1 + {\left\lbrack {\frac{1}{C_{IN}} + \frac{{1/C_{D}} + {1/\left( {C_{S/H} + C_{PP}} \right)}}{1 + {C_{P}/C_{D}} + {C_{P}/\left( {C_{S/H} + C_{PP}} \right)}}} \right\rbrack\left( {C_{GS} + C_{GD}} \right)}}}} & (42)\end{matrix}$Where, g_(M) and Z_(OUT) are respectively the transconductance of FET T₁and the impedance at the drain of the cascode FET T₃. The product ofg_(M) times Z_(OUT) will be adjusted to be greater than 10000 and thebandwidth adjusted in concert with the USSS pixel bandwidth to be lessthan 100 Hz.

The inverting amplifier readout circuit schematic, shown in FIG. 6, doesnot include provisions for removing the local threshold variations and1/f noise. Voltages from these sources produce errors that cannot bedistinguished from temperature differences between the detector andintermediate stage. Therefore it is very important to cancel localthreshold offsets and 1/f noise offset to achieve minimization ofthermal loading through the USSS electro-thermal feedback loop andthereby maximize sensitivity. It is desirable that this improvement bedone electronically without any mechanical choppers. A circuit withprovisions for removing local threshold variations and canceling the lowfrequency 1/f noise components is shown in FIG. 8. This circuit issymmetrically constructed with two common source MOS transistors T₁ andT₂ to cancel temperature dependence of the threshold voltage. The twodiodes 22 and 20, respectively, monitor the temperature of theintermediate and detector stages 16 and 14. A cascode stage T₃ is addedto minimize capacitive loading on the gate from the Miller effect.Switches S₁ and S₂ have been incorporated into the circuit in FIG. 6 forimplementing the CNC operation.

FIG. 8 is used to provide a detailed description of how the CNC circuitoperates. The cascode MOS transistor T₃ eliminates the Miller multiplierof the gate-to-drain capacitance from loading the signal provided by thetwo temperature sensing diodes 20 and 22 (Equation 42). The rest of thecircuit is constructed symmetrically like that of FIG. 6 to remove theMOS threshold offsets and the low frequency 1/f noise. Threshold and lowfrequency 1/f removal is facilitated with two low noise currentgenerators I_(H1) and I_(H2). The effect of threshold offsets and lowfrequency 1/f noise is removed by recording these signals on the sampleand hold capacitor S/H that removes them. This is illustrated byanalyzing the circuit operation of FIG. 8 in conjunction with theswitching sequence shown in FIG. 9.

Initially, cascade MOSFET T₃ is switched on hard to electrically shortthe output node 36 to the drain and source of the common gate MOStransistor T₃ by applying the S3 waveform shown in FIG. 9. Next, switchS₁ is turned on and this is followed by turning on switch S₂ as alsoillustrated in FIG. 9. This results in a symmetrical circuit about thesample and hold capacitor S/H. The left plate of the capacitor S/Hreceives voltage V_(IN2) and the right plate receives voltage V_(IN1).Voltage V_(IN1) includes the MOS threshold voltage V_(T1) and the noisevoltage E_(N1). Similarly, voltage V_(IN2) includes the MOS thresholdvoltage V_(T2) and the noise voltage E_(N2). Accordingly, the twovoltages applied across the capacitor S/H can be written as:V _(IN1) =−V _(T1) −E _(N1)(t)  (43)V _(IN2) =−V _(T2) −E _(N2)(t)The voltages generated on the drain of the MOS transistor T₂ results ina voltage V_(S/H) across the S/H capacitor which can be expressed as:V _(S/H)(t)=V_(T2) −V _(T1) +E _(N2)(t)−E _(N1)(t)  (44)The switching sequence for the circuit in FIG. 8 is illustrated in FIG.9 for a single period equal to the frame rate. Three pulses are used forswitching and the switching waveforms are nested: S2 is nested inside S1and S1 is nested inside S3. S3 represents the waveform applied to thecascode MOS T₃ to turn it hard so it becomes short. In the OFF position,T₃ is biased in a normal ON state so that it behaves as a common gateamplifier.

With the switches S₁ and S₂ ON, and the voltage given by Equation 44appears across the capacitor S/H, and a new equilibrium is establishedinside the circuit of FIG. 8. With switch S1, S2 and S3 ON, the voltageamplifier's gain is disabled and hence the electro-thermal feedback isdisabled.

This disabling of the electro-thermal feedback loop greatly reduces(×100) the thermal isolation of the detector stage 14 thereby causingthe temperature of detector stage 14 and intermediate stage 16temperature to converge and decrease towards the temperature of the heatbath stage 18 (FIG. 3). With the detector and intermediate stages 14 and16 at the same temperature, no voltage is produced across theback-to-back temperature sensing diodes 20 and 22. The gate voltageapplied to each MOS transistor T₁, T₂, and T₃ by the respective drainsis automatically adjusted to accommodate low noise current I_(H). Thus,the voltages applied to the MOS gates compensate (or cancel) theinternal MOS threshold and noise voltages. The voltage around the loopformed by the two MOS transistors gates T₁, and T₂, the two diodes 20and 22, and the S/H capacitor sums to zero.

The voltage across the capacitor S/H at time to is recorded whenswitches S1 and S2 are opened, and switch S3 waveform enables thecascode stage T₃. With these actions, the voltage amplifier T₁ isenabled and the electro-thermal feedback loop is made operational. Thisleads to a new equilibrium between the scene, the detector stage 14, andthe intermediate stage 16 (FIG. 3). The temperature of the back-to-backdiodes 20 and 22 changes and a voltage signal is produced to drive thevoltage amplifier T₁ with cascode stage T₂. This new differentialtemperature voltage signal is in series with the recorded voltage acrossthe capacitor S/H and the noise and threshold voltages associated witheach MOS transistor T₁ and T₂. Summing all these voltage terms, thevoltage V_(G)(t) applied to the gate of the voltage amplifier T₁ andrelative to T₂ is given by: $\begin{matrix}\begin{matrix}{{V_{G}(t)} = {V_{T1} - V_{T2} + {E_{N1}(t)} - {E_{N2}(t)} + {\delta\quad{V_{G}(t)}} + {V_{S/H}\left( t_{o} \right)}}} \\{= {{E_{N1}(t)} - {E_{N1}\left( t_{O} \right)} - {E_{N2}\left( t_{O} \right)} + {E_{N2}\left( t_{O} \right)} + {\delta\quad{V_{IN}(t)}}}}\end{matrix} & (45)\end{matrix}$

The voltage recorded on the capacitor S/H cancels the local thresholdvariations. Additionally, noise voltages are recorded on the capacitorS/H and these will modify the noise in the circuit. The noisemodification is better recognized in the frequency domain and thus isrepresented by the expression:V _(G)(ω)=E _(N1)(ω)└1−e ^(−iωt) ⁰ ┘−E _(N2)(ω)└1−e ^(−iωt) ⁰ ┘+δV_(IN)(ω)  (46)

The spectral content of the voltage applied to the gate V_(G)(ω) of T₁is made up of three terms: two noise terms and a signal term. Each ofthe noise term is expressed as a difference between the noise value at“t” and “t_(o)”. The time dependence of the noise is unknown, but we doknow how to represent noise by its power spectral density. Using thisrepresentation, the noise contribution to the signal in Equation 46 isreadily expressed and is given by: $\begin{matrix}{{V_{G}(t)} = {{\delta\quad{V_{IN}(t)}} + \sqrt{{\int_{- \infty}^{\infty}{{{E_{N1}(\omega)}}^{2}\quad{\sin^{2}\left\lbrack \frac{\omega\quad t_{O}}{2} \right\rbrack}\quad{\mathbb{d}\omega}}} + {\int_{- \infty}^{\infty}{{{E_{N2}(\omega)}}^{2}\quad{\sin^{2}\left\lbrack \frac{\omega\quad t_{O}}{2} \right\rbrack}\quad{\mathbb{d}\omega}}}}}} & (47)\end{matrix}$

It is evident from Equation 47 that the voltage amplifier noise ismodified by a sine-squared term and this term will suppress thecontribution of low frequency 1/f noise and double the power of thewhite noise. The reduction of the 1/f noise depends on the amplifierbandwidth and the time difference between sampling the noise and readingof the signal, or correlation. The time difference between reading thesignal and noise is t_(o)/2. Hence, noise terms with frequencies varyingslower than t_(o)/2 will be attenuated. Noise frequencies beyond thiswill be increased, depending on the amplifier's bandwidth.

Determination of the noise power will now be made. The noise from theUSSS electrical readout circuit is affected by CNC and electro-thermalfeedback. Equation 46 provides an expression for the effect of the CNCon the noise's spectral amplitude without including any other effects.However, the noise's is also modified by the electro-thermal feedbackand the voltage amplifier's frequency response. Both of these effectsare incorporated into a model and an analytical expression is obtainedthat includes these effects. The analysis makes use of superposition ofthe different frequency components of the noise. We do not know thespecific value of the noise amplitude is not known since these arealgebraic variables. Once the linear analysis is completed with thenoise amplitude, the results are transformed into a power spectraldensity and integrated to compute the total RMS noise value. The noisepower spectral density of the electrical circuits is something that isroutinely measured and the calculated analytical results can benumerically evaluated in terms of these experimental measurements.

The effective total spectral noise voltage V_(NO)(ω) (applied to the MOSgate of the voltage amplifier T₁ without including any form of feedbackis given by Equation 46 if the signal δV_(IN)(ω) is removed and isdefined as:V _(NO)(ω)=E _(N1)(ω)└1−e ^(−iωt) ⁰ ┘−E _(N2)(ω)└1−e ^(−iωt) ⁰ ┘  (48)

Electro-thermal feedback produces this noise level and the noise voltageis modified to V_(N)(ω) from V_(NO)(ω) and these are related by theexpression: $\begin{matrix}\begin{matrix}{{{V_{NO}(\omega)} + {\delta\quad{E_{IN}(\omega)}}} = {{V_{NO}(\omega)} + {\frac{\partial\left\lbrack {\Delta\quad{\Phi_{IN}\left( T_{IN} \right)}} \right\rbrack}{\partial T_{IN}}\delta\quad{T_{IN}(\omega)}} -}} \\{\frac{\partial\left\lbrack {\Delta\quad{\Phi_{D}\left( T_{D} \right)}} \right\rbrack}{\partial T_{D}}\quad\delta\quad{T_{D}(\omega)}} \\{= {{V_{NO}(\omega)} + {\frac{\partial\left\lbrack {\Delta\quad{\Phi_{IN}\left( T_{IN} \right)}} \right\rbrack}{\partial T_{IN}}\left\lbrack {{\delta\quad{T_{IN}(\omega)}} - {\delta\quad{T_{D}(\omega)}}} \right\rbrack}}} \\{= {V_{N}(\omega)}}\end{matrix} & (49)\end{matrix}$

The expression for δE_(IN)(ω) in Equation 49 was obtained from Equations14 and 42, 50. Also, the temperature derivative ∂ΔΦ(T)/∂T of thepotential difference across the diodes 20 and 22 is the same for thedetector and intermediate stages 14 and 16. Thus Equation 49 simplyreflects the fact that changing noise voltage on the gate will slightlychange the MOS amplifier current and this will cause a slight change inthe intermediate stage 16.

A detailed qualitative examination of the circuit shown in FIG. 8reveals the effects of electro-thermal feedback on the noise voltageamplitude. Specifically, the sequence of events that occurs if the noiseamplitude increases at the gate of MOS T₁′ as follows:

-   -   1. Noise at the gate of MOS T₁′ increases.    -   2. Larger voltage on MOS gate T₁′ reduces current flowing in the        MOS channel of T₁′.    -   3. The output voltage becomes more negative.    -   4. With a bigger drop across drain to source of T₁′ causes the        amplifier's quiescent power to increase thereby heating the        intermediate stage.    -   5. The temperature of the intermediate stage 16 increases        slightly.    -   6. The intermediate stage diode 22 temperature sensor decreases        its output voltage.    -   7. The voltage on MOS gate T₁′ decreases slightly to compensate        for the increases in noise voltage.

If the noise voltage at the gate of T₁′ decreases, then the reverse willoccur in the aforementioned steps 1 though 7. What is important to noteis that the sequence detailed above shows that electro-thermal feedbackreduces the amplitude of the noise voltage. This qualitative explanationis corroborated by the following analysis.

Relating the noise with electro-thermal feedback [V_(N)(ω)] to the noisewithout feedback electro-thermal feedback [V_(NO)(ω)] requiresevaluating Equation 49 and specifically requires computation of δT_(IN)and δT_(D), since ∂ΔΦ(T)/∂T is known from Equation 42. The relationshipbetween δT_(IN) and δT_(D) is readily obtained from Equations 4. Usingsuperposition, the change in temperature of the intermediate stage interms of changes in the temperature of the detector stage is given byEquation 4 when δT_(S) is zero. After doing the algebra, the followingexpression is obtained: $\begin{matrix}{{\delta\quad T_{D}} = {\frac{\left\lbrack G_{2} \right\rbrack}{\left\lbrack {G_{D1} + G_{2} + {j\quad\omega\quad C_{D}}} \right\rbrack}\quad\delta\quad T_{IN}}} & (50)\end{matrix}$

Change in quiescent heat delivered induced by the gate noise voltage T₁′is given as δQ_(H)=I_(H)Z_(O)V_(N)(ω)g_(M), where Z_(O) is the outputimpedance of the MOS/cascode voltage amplifier and g_(M) is thetransconductance of this amplifier. Substituting this for δQ_(H) inEquation 5, and after some rearrangement an expression is obtained whichcan be expressed as:−[G _(D2) +G ₂ +G ₃ +jωC _(IN) ]δT _(IN) +G ₂ δT _(D) +I _(H) Z _(O) V_(N)(ω)g _(M)=0  (51)

Changes in the temperature of the intermediate stage 16 is readilycomputed in terms of the noise voltage by substituting Equation 50 intoEquation 51, and solving for δT_(IN), obtained is: $\begin{matrix}{{\delta\quad{T_{IN}(\omega)}} = \frac{I_{H}Z_{O}{V_{N}(\omega)}\quad{g_{M}\left\lbrack {G_{D1} + G_{2} + {j\quad\omega\quad C_{D}}} \right\rbrack}}{{G_{2}\left( {G_{D1} + {j\quad\omega\quad C_{D}}} \right)} + {\left( {G_{D2} + G_{3} + {j\quad\omega\quad C_{IN}}} \right)\left( {G_{D1} + G_{2} + {j\quad\omega\quad C_{D}}} \right)}}} & (52)\end{matrix}$

Substituting Equation 50 for δT_(D) in Equation 49 and replacing δT_(IN)with Equation 52 a resulting expression for the resulting MOS gate noisevoltage modified by electro-thermal feedback in terms of the initialnoise voltage without feedback is given by: $\begin{matrix}\begin{matrix}{{V_{N}(\omega)} =} \\{\quad\frac{V_{NO}(\omega)}{\left\lbrack {1 + \frac{{- I_{H}}Z_{O}g_{M}{\frac{\partial\left\lbrack {\Delta\quad{\Phi_{IN}(\omega)}} \right\rbrack}{\partial T_{IN}}\left\lbrack {G_{D1} + {j\quad\omega\quad C_{D}}} \right\rbrack}}{{G_{2}\left( {G_{D1} + {j\quad\omega\quad C_{D}}} \right)} + {\left( {G_{D2} + G_{3} + {j\quad\omega\quad C_{IN}}} \right)\left( {G_{D1} + G_{2} + {j\quad\omega\quad C_{D}}} \right)}}} \right\rbrack}}\end{matrix} & (53)\end{matrix}$

Electro-thermal feedback decreased the noise amplitude and this isevident from the denominator of Equation 53, which is greater than one.The noise reduction depends on the size of the magnitude of thealgebraic expression in the denominator. However, it is evident that thebetter the thermal isolation is of the detector stage 14 from theintermediate stage 16, and the intermediate stage 16 from the heat bath18, the lower will be the noise from the readout circuit.

Therefore, designing a USSS based bolometer requires care to be taken soas to minimize G₂, and G₃ so that maximum performance can be achieved.

Incorporating Equation 53 into Equation 47 yields an expression for thenoise and signal applied to the USSS MOS readout amplifier withelectro-thermal feedback effects included and can be expressed as:$\begin{matrix}{{V_{G}(t)} = {{\delta\quad{V_{IN}(t)}} + \sqrt{\int_{- \infty}^{\infty}{{{V_{N}(\omega)}}^{2}\quad{\sin^{2}\left\lbrack \frac{\omega\quad t_{O}}{2} \right\rbrack}\quad{\mathbb{d}\omega}}}}} & (54)\end{matrix}$

As mentioned previously, the CNC suppresses the low frequency 1/f noisecomponents since the sine squared term inside the integral of Equation54 provides an “ω²” term that cancels the divergence from the 1/f noise.The output noise voltage from the voltage amplifier T₁″ depends on thetransconductance and the output impedance and becomes: $\begin{matrix}{{V_{O}(t)} = {g_{M}\quad{Z_{O}\left\lbrack {{\delta\quad{V_{IN}(t)}} + \sqrt{\int_{- \infty}^{\infty}{{{V_{N}(\omega)}}^{2}\quad{\sin^{2}\left\lbrack \frac{\omega\quad t_{O}}{2} \right\rbrack}\quad{\mathbb{d}\omega}}}} \right\rbrack}}} & (55)\end{matrix}$

The evaluation of the integral inside the square brackets requires useof exponential integrals and these have been tabulated but are not shownfor sake of brevity.

Instead of using inverting amplifiers as illustrated in FIGS. 6 and 8for a pixel 10 _(a), a USSS pixel 10 _(b) can be also implemented withnon-inverting amplifiers. Such an embodiment and analysis is presentednext.

An electro-thermal feedback amplifier with the threshold and 1/f noisecancellation elements is shown in FIG. 10. This circuit includes anon-inverting voltage amplifier, two temperature sensors 20 and 22. Thenon-inverting voltage amplifier includes FET transistors T₁″ and T₂″ toachieve a high input impedance circuit for reading the two diodetemperature sensors. The detector stage's 14 temperature sensor is diode20 and the intermediate stage's 16 temperature sensor is a second diode22. The temperature dependent threshold voltage of the FET T₁″ iscancelled with FET T₂″. Both temperature sensing diodes 20 and 22 andthe FETs T₁″ and T₂″ have the same temperature characteristics. This isimportant for the operation of the electro-thermal feedback loop. Theeffectiveness of the electro-thermal feedback loop depends on theamplifier's voltage gain made from FET T₁″. Specifically, theamplifier's output voltage V(OUT) depends on the voltage gain and thevoltage difference stemming from the temperature difference between thetwo back-to-back diode thermocouples 20 and 22.

A physical layout is needed to provide circuit realism for analyzing theoutput voltage V(OUT) and this is achieved with the aid of an equivalentcircuit that includes relevant parasitics. FIG. 11 is an equivalentcircuit for circuit in FIG. 10 with parasitic capacitances included. Theworst case affects of parasitic capacitances are at high frequencies.The analysis includes these even though the circuit operates at very lowfrequencies where conventionally parasitic capacitances do not matter.However, because the diode thermocouples 20 and 22 have high impedances,they are treated as charged capacitors C_(D) and C_(IN) biased withvoltages dependent on temperature. With sufficiently large timeconstants, parasitic capacitances do matter.

As before in the case of FIG. 8, the FET non-inverting electro-thermalfeedback circuit, illustrated in FIG. 10, incorporates provisions fortemperature sensing and electro-thermal feedback to equalize thetemperatures of the intermediate stage 16 with the temperature of thedetector stage 14.

The analysis of FIG. 10 provides the output voltage V(OUT) as a functionof changes in the voltage across the detector's and intermediate'sstages diode thermocouples 20 and 22. The total signal from the twodiode thermocouples is calculated using superposition to solve for theV(OUT) in terms of the voltage across the detector and intermediatediode thermocouples. Analysis shows the significance of parasiticcapacitances. Proper operation of the electro-thermal feedback looprequires the transfer function for the detector and intermediate stagetemperature sensing diodes 20 and 22 other than signs to be the same.Deriving the output voltage produced by the detector's stage diodethermocouple 20 is computed first.

The equivalent circuit of the circuit diagram of FIG. 10 is shown inFIG. 11. The equivalent circuit of FIG. 11 depicts FET T₁″ as anamplifier with voltage gain G, where G approaches unity. The outputimpedance of FET T₁″ is much lower than any of the capacitive elementsand is approximated as zero. The threshold voltage of FET T₁″ isrepresented as V_(IN1). Similarly, the impedance of FET T₂″ is also verysmall and it is represented as a voltage generator corresponding to thethreshold voltage of T₂″, i.e., V_(IN2). There are several parasiticcapacitances and these are included in the analysis. Capacitance C_(P)is the parasitic capacitance from the intermediate stage temperaturesensing diode 22 to the N+ backside contact. Capacitance C_(PP) is theparasitic capacitance from the detector stage temperature sensing diode20 to the substrate. Capacitance C_(GD) is the parasitic capacitancebetween the gate of FET T₁″ and its the drain. Capacitance C_(GS) is theparasitic capacitance between the gate of FET T₁″ and the source. Theanalysis of this circuit is performed using capacitors as shown in FIG.11 because the two zero current bias temperature sensing diodes 20 and22 are best represented by capacitors C_(D) and C_(IN) with a chargeacross that changes with temperature. For the purpose of clarity, theanalysis begins without including CNC switches.

Three-charge currents δq₁, δq₂, and δq₃, are produced by temperaturechanges in the of the two sensing diode thermocouples 20 and 22, nowrepresented by capacitors C_(D) and C_(IN). Mesh equations for each oneof these three charge currents δq₁, δq₂, and δq₃ are expressed as:V _(IN1) −V _(GS) −V _(P) +V _(IN)=0  (56)V _(IN2) +V _(D) −V _(P) −V _(S/H)=0  (57)V _(IN1) −V _(D) +V _(IN) +V _(PP) −V _(G)=0  (58)

Under equilibrium, the voltages across capacitors C_(D) and C_(IN) arerepresented as a ratio of the charge divided by its capacitance. Makingthese substitutions, Equation 56, 57 and 58 are rewritten to yield:$\begin{matrix}{{V_{IN1} - V_{GS} - \frac{Q_{P}}{C_{P}} + \frac{Q_{IN}}{C_{IN}}} = 0} & (59) \\{{V_{IN2} + \frac{Q_{D}}{C_{D}} - \frac{Q_{P}}{C_{P}} - \frac{Q_{S/H}}{C_{S/H}}} = 0} & (60) \\{{V_{IN1} - \frac{Q_{D}}{C_{D}} + \frac{Q_{IN}}{C_{IN}} + \frac{Q_{PP}}{C_{PP}} - V_{G}} = 0} & (61)\end{matrix}$

Equations 59 through 61 represent FIG. 11 after equilibrium isreestablished from an arbitrary set of initial conditions. The effect oftemperature changes in the detector stage 14, and the intermediate stage16, are analyzed next.

Temperature changes in the detector stage's 14 will change the charge onthe detector temperature sensing diode 20 by ΔQ_(D). This will unbalancethe voltages around the closed loops illustrated in FIG. 11 and causecharge currents δq₁, δq₂, and δq₃ to flow so that a new equilibrium isestablished. Rewriting Equations 59 through 61 the new equilibriumconditions are obtained and these are given by: $\begin{matrix}{{V_{IN1} - V_{GS} - {\delta\quad V_{GS}} - \frac{\left( {Q_{P} + {\delta\quad q_{1}} + {\delta\quad q_{2}}} \right)}{C_{P}} + \frac{\left( {Q_{IN} - {\delta\quad q_{1}} - {\delta\quad q_{3}}} \right)}{C_{IN}}} = 0} & (62) \\{{{{- \delta}\quad V_{GS}} - \frac{\left( {{\delta\quad q_{1}} + {\delta\quad q_{2}}} \right)}{C_{P}} - \frac{\left( {{\delta\quad q_{1}} + {\delta\quad q_{3}}} \right)}{C_{IN}}} = 0} & \quad \\{{V_{IN2} + \frac{\left( {Q_{D} + {\Delta\quad Q_{D}} - {\delta\quad q_{2}} + {\delta\quad q_{3}}} \right)}{C_{D}} - \frac{\left( {Q_{P} + {\delta\quad q_{1}} + {\delta\quad q_{2}}} \right)}{C_{P}} - \frac{\left( {Q_{S/H} + {\delta\quad q_{2}}} \right)}{C_{S/H}}} = 0} & (63) \\{{\frac{\left( {{\Delta\quad Q_{D}} - {\delta\quad q_{2}} + {\delta\quad q_{3}}} \right)}{C_{D}} - \frac{\left( {{\delta\quad q_{1}} + {\delta\quad q_{2}}} \right)}{C_{P}} - \frac{\delta\quad q_{2}}{C_{S/H}}} = 0} & \quad \\{{V_{IN1} - \frac{\left( {Q_{D} + {\Delta\quad Q_{D}} - {\delta\quad q_{2}} + {\delta\quad q_{3}}} \right)}{C_{D}} + \frac{\left( {Q_{IN} - {\delta\quad q_{3}} - {\delta\quad q_{1}}} \right)}{C_{IN}} + \frac{\left( {Q_{PP} - {\delta\quad q_{3}}} \right)}{C_{PP}} - V_{G} - {\delta\quad V_{G}}} = 0} & (64) \\{{{- \frac{\left( {{\Delta\quad Q_{D}} - {\delta\quad q_{2}} + {\delta\quad q_{3}}} \right)}{C_{D}}} - \frac{\left( {{\delta\quad q_{3}} + {\delta\quad q_{1}}} \right)}{C_{IN}} - \frac{\delta\quad q_{3}}{C_{PP}} - {\delta\quad V_{G}}} = 0} & \quad\end{matrix}$

The second line in each equation has been obtained by using Equations 59through 61 to remove the terms in each equation that sum up to zero. Anexpression for changes in the output voltage V(OUT) in response to achange of ΔQ_(D) is obtained in terms of currents δq₁, δq₂, and δq₃. Theoutput voltage V(OUT) given in terms of changes currents δq₁, δq₂, andδq₃ is given by: $\begin{matrix}{{\delta\quad V_{GS}} = {{{\delta\quad V_{G}} - {G\quad\delta\quad V_{G}}} = \frac{\left( {{\delta\quad q_{1}} + {\delta\quad q_{3}}} \right)\left( {1 - G} \right)}{C_{GD} + {\left( {1 - G} \right)\quad C_{GS}}}}} & (65)\end{matrix}$

Utilizing Equation 65 we eliminate the variables δV_(G), and δV_(GS) inEquations 62, and 64, to obtain a solution for δq₁, and δq₃ in terms ofΔQ_(D) and the equivalent circuit parameters and parasitic capacitancesshown in FIG. 11. Replacing variables δV_(G), and δV_(GS), in Equations62, and 64 with Equation 65 and grouping terms a new set of equationsare obtained which are given by: $\begin{matrix}{{{\left\lbrack {\frac{\left( {1 - G} \right)}{C_{GD} + {\left( {1 - G} \right)\quad C_{GS}}} + \frac{1}{C_{P}} + \frac{1}{C_{IN}}} \right\rbrack\quad\delta\quad q_{1}} + {\left\lbrack \quad\frac{1}{C_{P}} \right\rbrack\quad\delta\quad q_{2}} + {\left\lbrack {\frac{\left( {1 - G} \right)}{C_{GD} + {\left( {1 - G} \right)\quad C_{GS}}} + \frac{1}{C_{IN}}} \right\rbrack\quad\delta\quad q_{3}}} = 0} & \left( {62a} \right) \\{{{{\left\lbrack \frac{1}{C_{P}} \right\rbrack\quad\delta\quad q_{1}} + {\left\lbrack {\frac{1}{C_{D}} + \frac{1}{C_{P}} + \frac{1}{C_{S/H}}} \right\rbrack\quad\delta\quad q_{2}} - {\left\lbrack \frac{1}{C_{D}} \right\rbrack\quad\delta\quad q_{3}}} = {\frac{\Delta\quad Q_{D}}{C_{D}} - {\left\lbrack {\frac{1}{C_{IN}} + \frac{1}{C_{GD} + {\left( {1 - G} \right)\quad C_{GS}}}} \right\rbrack\quad\delta\quad q_{1}} + \left\lbrack \frac{1}{C_{D}} \right\rbrack}}\quad{{{\delta\quad q_{2}} - {\left\lbrack \quad{\frac{1}{C_{D}} + \frac{1}{C_{IN}} + \frac{1}{C_{PP}} + \frac{1}{C_{GD} + {\left( {1 - G} \right)C_{GS}}}} \right\rbrack\quad\delta\quad q_{3}}} = \frac{\Delta\quad Q_{D}}{C_{D}}}} & \left( {63a} \right)\end{matrix}$

Solving for δq₁, and δq₃ requires first replacing δq₂ in Equations 63aand 64a using Equation 62a. Once Equations 63a and 64a have eliminatedthe variable δq₂, δq₁, and δq₃ can be solved in terms of ΔQ_(D).Inserting these terms into Equation 65, an expression for V(OUT) interms of ΔQ_(D) is obtained. Rewriting Equation 62 to solve for δq₂ interms of δq₁, and δq₃, obtained is: $\begin{matrix}{{\delta\quad q_{2}} = {{{- \left\lbrack {\frac{\left( {1 - G} \right)\quad C_{P}}{C_{GD} + {\left( {1 - G} \right)\quad C_{GS}}} + \frac{C_{P}}{C_{IN}} + 1} \right\rbrack}\delta\quad q_{1}} - {\left\lbrack {\frac{\left( {1 - G} \right)\quad C_{P}}{C_{GD} + {\left( {1 - G} \right)\quad C_{GS}}} + \frac{C_{P}}{C_{IN}}} \right\rbrack\quad\delta\quad q_{3}}}} & \left( {62b} \right)\end{matrix}$

Substituting 62b into 63a, a new Equation after some regrouping of termsis obtained, and it is given by: $\begin{matrix}{{{\left\lbrack {{\left( {\frac{1}{C_{D}} + \frac{1}{C_{P}} + \frac{1}{C_{S/H}}} \right)\left( {\frac{C_{P}\left( {1 - G} \right)}{C_{GD} + {\left( {1 - G} \right)\quad C_{GS}}} + \frac{C_{P}}{C_{IN}}} \right)} + \frac{1}{C_{D}} + \frac{1}{C_{S/H}}} \right\rbrack\delta\quad q_{1}} + {\left\lbrack {{\left( {\frac{1}{C_{D}} + \frac{1}{C_{P}} + \frac{1}{C_{S/H}}} \right)\left( {\frac{C_{P}\left( {1 - G} \right)}{C_{GD} + {\left( {1 - G} \right)\quad C_{GS}}} + \frac{C_{P}}{C_{IN}}} \right)} + \frac{1}{C_{D}}} \right\rbrack\delta\quad q_{3}}} = {- \frac{\Delta\quad Q_{D}}{C_{D}}}} & (66)\end{matrix}$

Substituting 62b into 64a, a second equation after some regrouping isobtained and it is given by: $\begin{matrix}{{{\left\lbrack \left( {\frac{1}{C_{GD} + {\left( {1 - G} \right)\quad C_{GS}}} + \frac{1}{C_{IN}} + \frac{1}{C_{PP}} + {\left( {\frac{C_{P}\left( {1 - G} \right)}{C_{GD} + {\left( {1 - G} \right)\quad C_{GS}}} + \frac{C_{P}}{C_{IN}}} \right)\quad\frac{1}{C_{D}}}} \right) \right\rbrack\delta\quad q_{1}} + {\left\lbrack {\frac{1}{C_{GD} + {\left( {1 - G} \right)\quad C_{GS}}} + \frac{1}{C_{IN}} + \frac{1}{C_{D}} + \frac{1}{C_{PP}} + {\left( {\frac{C_{P}\left( {1 - G} \right)}{C_{GD} + {\left( {1 - G} \right)\quad C_{GS}}} + \frac{C_{P}}{C_{IN}}} \right)\quad\frac{1}{C_{D}}}} \right\rbrack\delta\quad q_{3}}} = {- \frac{\Delta\quad Q_{D}}{C_{D}}}} & (67)\end{matrix}$

Combining Equations 66 and 67 with Equation 65 a simplified expressionfor V(OUT) in terms of ΔQ_(D) is obtained if one recognizes thatC_(D)<<C_(S/H).

Using Equation 65 in conjunction with Equation 66 an expression forV(OUT)=δV_(S)=GδV_(G) is obtained and it is given by: $\begin{matrix}{{\delta\quad V_{S}} = {{- \left( \frac{\Delta\quad Q_{D}}{C_{D}} \right)}\frac{G}{\begin{matrix}\left\lbrack {{\left( {\frac{1}{C_{D}} + \frac{1}{C_{P}} + \frac{1}{C_{S/H}}} \right)\left( {\frac{\left( {1 - G} \right)C_{P}}{C_{GD} + {\left( {1 - G} \right)\quad C_{GS}}} + \frac{C_{P}}{C_{IN}}} \right)} + \frac{1}{C_{P}}} \right\rbrack \\\left\lbrack {C_{GD} + {\left( {1 - G} \right)C_{GS}}} \right\rbrack\end{matrix}}}} & (68)\end{matrix}$The structure of Equation 68 includes a leading factor that is equal tothe detector stage 14 thermocouple voltage times several numericalterms. Evaluating these, the relative value of the terms is nextutilized in Equation 68. By design, it can be seen that C_(GS)≅C_(GD),C_(S/H)>>{C_(D), C_(IN)}, and C_(D)≅C_(G), G≅1, and C_(P)>>C_(IN).Including these in Equation 68, a simplified expression forV(OUT)=δV_(S)=GδV_(G) is obtained and it is given by: $\begin{matrix}{{\delta\quad V_{S}} \cong {{- \left( \frac{\Delta\quad Q_{D}}{C_{D}} \right)}\left( \frac{C_{D}}{2C_{GD}} \right)}} & (69)\end{matrix}$

This expression illustrates that the gain of the non-inverting voltageamplifier for signals applied to the FET's T₁″ gate can be approximatedas the ratio between the detector thermocouple diode 20 capacitanceC_(D) divided by twice the FET's parasitic gate to drain capacitanceC_(GD). The estimated value of C_(GD)≅0.5 fF and this will limit thegain of the amplifier to about 90. To achieve larger gain, the value ofC_(GD)≅0.5 fF needs to be reduced or additional gain stages must beinserted.

Now computing the output voltage signal V(OUT)=δV_(S)=GδV_(G) due tochanges in the intermediate stage diode thermocouple voltage the sameequivalent circuit given in FIG. 11 is used. However, instead ofassuming a change in the detector stage diode thermocouple, it isassumed that the intermediate stage thermocouple 22 has experienced atemperature change resulting in a charge change of ΔQ_(IN). Writing theequations was done for the detector stage (see Equation 56 through 61)and after some simplifications, the following expressions result:$\begin{matrix}{{{{- \delta}\quad V_{GS}} - \frac{\left( {{\delta\quad q_{1}} + {\delta\quad q_{2}}} \right)}{C_{P}} + \frac{\left( {{\Delta\quad Q_{IN}} - {\delta\quad q_{1}} - {\delta\quad q_{3}}} \right)}{C_{IN}}} = 0} & (70) \\{{\frac{{{- \delta}\quad q_{2}} + {\delta\quad q_{3}}}{C_{D}} - \frac{{\delta\quad q_{1}} + {\delta\quad q_{2}}}{C_{P}} - \frac{\delta\quad q_{2}}{C_{S/H}}} = 0} & (71) \\{{\frac{{\delta\quad q_{2}} - {\delta\quad q_{3}}}{C_{D}} + \frac{\left( {{\Delta\quad Q_{IN}} - {\delta\quad q_{3}} - {\delta\quad q_{1}}} \right)}{C_{IN}} - \frac{\delta\quad q_{3}}{C_{PP}} - {\delta\quad V_{G}}} = 0} & (72)\end{matrix}$

Equation 70 corresponds to Equation 62, Equation 71 corresponds toEquation 63 and Equation 72 corresponds to Equation 64. UtilizingEquation 65, the δV_(G) and δV_(GS) terms can be eliminated and aftersome rearrangements and grouping of terms one obtains: $\begin{matrix}{{{\left\lbrack {\frac{1 - G}{C_{GD} + {\left( {1 - G} \right)C_{GS}}} + \frac{1}{C_{P}} + \frac{1}{C_{IN}}} \right\rbrack\quad\delta\quad q_{1}} + \frac{\delta\quad q_{2}}{C_{P}} + {\left\lbrack {\frac{1 - G}{C_{GD} + {\left( {1 - G} \right)\quad C_{GS}}} + \frac{1}{C_{IN}}} \right\rbrack\quad\delta\quad q_{3}}} = \frac{\Delta\quad Q_{IN}}{C_{IN}}} & \left( {70a} \right) \\{{\frac{\delta\quad q_{1}}{C_{P}} + {\left\lbrack {\frac{1}{C_{D}} + \frac{1}{C_{P}} + \frac{1}{C_{S/H}}} \right\rbrack\quad\delta\quad q_{2}} - \frac{\delta\quad q_{3}}{C_{D}}} = 0} & \left( {71a} \right) \\{{{\left\lbrack {\frac{1}{C_{GD} + {\left( {1 - G} \right)\quad C_{GS}}} + \frac{1}{C_{IN}}} \right\rbrack\quad\delta\quad q_{1}} - \frac{\delta\quad q_{2}}{C_{D}} + {\left\lbrack {\frac{1}{C_{GD} + {\left( {1 - G} \right)\quad C_{GS}}} + \frac{1}{C_{D}} + \frac{1}{C_{PP}} + \frac{1}{C_{IN}}} \right\rbrack\quad\delta\quad q_{3}}} = \frac{\Delta\quad Q_{IN}}{C_{IN}}} & \left( {72a} \right)\end{matrix}$

The variable δq₂ is eliminated in Equations 70a and 72a by usingEquation 71a. Solving Equation 71a for δq₂ in terms of variables δq₁ andδq₃, and using this expression to eliminate δq₂ in Equations 70a and72a, after some rearrangements, two Equations for 70a and 72a areobtained and these are: $\begin{matrix}{{\left\lbrack {\frac{\left( {1 - G} \right)}{C_{GD} + {\left( {1 - G} \right)\quad C_{GS}}} + \frac{1}{C_{IN}} + \frac{{1/C_{D}} + {1/C_{S/H}}}{1 + {C_{P}/C_{D}} + {C_{P}/C_{S/H}}}} \right\rbrack\quad\delta\quad q_{1}} +} & \left( {70b} \right) \\{\quad{{\left\lbrack {\frac{\left( {1 - G} \right)}{C_{GD} + {\left( {1 - G} \right)C_{GS}}} + \frac{1}{C_{IN}} + \frac{1/C_{D}}{1 + {C_{P}/C_{IN}} + {C_{P}/C_{S/H}}}} \right\rbrack\quad\delta\quad q_{3}} = \frac{\Delta\quad Q_{IN}}{C_{IN}}}} & \quad \\{{\left\lbrack {\frac{1}{C_{GD} + {\left( {1 - G} \right)\quad C_{GS}}} + \frac{1}{C_{IN}} + \frac{1/C_{P}}{1 + {C_{D}/C_{P}} + {C_{D}/C_{S/H}}}} \right\rbrack\quad\delta\quad q_{1}} +} & \left( {72b} \right) \\{\quad\left\lbrack {\frac{1}{C_{GD} + {\left( {1 - G} \right)C_{GS}}} + \frac{1}{C_{D}} + \frac{1}{C_{PP}} + \frac{1}{C_{IN}} +} \right.} & \quad \\{{\left. \quad\frac{1/C_{D}}{1 + {C_{D}/C_{P}} + {C_{D}/C_{S/H}}} \right\rbrack\quad\delta\quad q_{3}} = \frac{\Delta\quad Q_{IN}}{C_{IN}}} & \quad\end{matrix}$

Examining Equations 70b and 72b, and comparing these to Equations 66 and67, respectively, similarities are noted. In the limit where{C_(PP),C_(P)}<<{C_(D),C_(IN)}<<C_(S/H), and{C_(GD),C_(GS)}<<{C_(D)≅C_(IN)}, the two equations pairs becomeidentical, except for a sign. The difference in sign results because thethermocouple temperature sensing diodes 20 and 22 are back to back toprovide a voltage signal representing the temperature difference betweenthe detector and intermediate stages 14 and 16. Thus the output signalfrom the non-inverting voltage amplifier made from FET T₁″ and T₂″ willbe a function of the temperature difference between the two thermocouplediodes 20 and 22 and will be amplified according to the expression:$\begin{matrix}{{\delta\quad V_{S}} \cong {\left( \frac{C_{D}}{2C_{GD}} \right)\left( {\frac{\Delta\quad Q_{IN}}{C_{IN}} - \frac{\Delta\quad Q_{D}}{C_{D}}} \right)}} & (73)\end{matrix}$

The gain represented by the leading factor of Equation 73 is limited bythe parasitic gate to drain capacitance of FET T₁″. The voltage gainwill be about 100. This may be sufficient for LWIR USSS cameras but notfor MM and THz USSS cameras.

The USSS readout circuit shown in FIGS. 10 and 11 do not includeprovisions for removing the local threshold variations and 1/f noise.Voltage offsets from these sources produce errors that cannot bedistinguished from temperature differences between the detector andintermediate stage 14 and 16. Therefore, it is very important to cancellocal threshold offsets and low frequency 1/f noise components tominimize thermal loading through the USSS electro-thermal feedback loopand thereby maximize sensitivity.

This improvement needs to be done electronically without any mechanicalchoppers. A circuit with the provisions for removing the local thresholdvariations and canceling the low frequency 1/f noise components is shownin FIG. 12.

Referring now to FIG. 12, the circuit is symmetrically constructed withtwo common source FET transistors T₁″ and T₂″ to cancel temperaturedependence of the threshold voltage. As before, the two diodes 20 and 22monitor the temperature of the intermediate and detector stages 14 and16.

The circuit of FIG. 12 is also constructed symmetrically to remove thethreshold offsets, mobility variations with temperature, and the lowfrequency 1/f noise. Threshold and low frequency 1/f removal isfacilitated with two low noise current generators I_(H) and 2I_(H). Theeffect of threshold offsets and low frequency 1/f noise is removed byrecording these on the sample and hold capacitor S/H that removes them.

This is mathematically illustrated by analyzing the circuit operation inconjunction with the switching sequence shown in FIG. 13. It begins bydisabling the “AC” coupled input of the antenna 30 (FIG. 3) to thedetector stage 14 and this is achieved by an electronic switch, notshown. Next, switch S₁ is turned ON and this is followed by turning ONswitch S₂ as illustrated in FIG. 13. Switch S₁, however, is optional andmay be entirely left out of the circuit when desired. Closing theseswitches forms a symmetric circuit about the capacitor S/H. The leftplate of the capacitor S/H receives voltage V_(IN2)(t) and the rightplate receives voltage V_(IN1)(t). Voltage V_(IN1)(t) include the FETthreshold voltage V_(T1) and the noise voltages E_(N1)(t). Similarly,voltage E_(N2)(t) includes the FET threshold voltage V_(T2) and thenoise voltages E_(N2)(t). Thus, the two voltages applied across theplates of capacitor S/H are expressed as:V _(IN1) =V _(T1) −E _(N1)(t)  (74)V _(IN2) =V _(T2) −E _(N2)(t)

With respect to FIG. 12, the circuit shown in FIG. 10 has electronicswitches S₁ and S₂ incorporated for implementing the cancellation oflocal threshold voltage variations and low frequency 1/f noisecomponents. Operation of this circuit with switches has been explainedheretofore.

A negative voltage is required to turn them ON. The sign in front ofnoise voltages E_(N1)(t) and E_(N2)(t) does not matter since thesevariable can be adjusted to account for the sign. The voltages generatedon the drains of the two FET transistors T₁″ and T₂″ result in a voltageV_(S/H) across the sample and hold capacitor S/H that can be expressedas:V _(S/H)(t)=V _(T1) −V _(T2) +E _(N2)(t)−E _(N1)(t)  (75)

With the switches S₁ and S₂ ON, and given the voltage given by Equation75 across the capacitor, a new equilibrium is established inside thecircuit shown in FIG. 12. With switch S₁, and S₂ ON, the voltageamplifier's gain is disabled and hence the electro-thermal feedback isdisabled. Additionally, a separate switch can be used to disable theantenna input to the detector stage. The combination of disabling theelectro-thermal feedback loop and the antenna input greatly reduces(×100) the detector stage's thermal isolation and signal causing thetemperature of the detector and intermediate stages 14 and 16 convergeand decrease towards the temperature of the heat bath 18. With thedetector and intermediate stages 14 and 16 at the same temperature, novoltage is produced across the back-to-back temperature sensing diodes20 and 22. The gate voltage applied to each FET transistor T₁″ and T₂″by the respective drains is automatically adjusted to accommodate lownoise current in I_(H), and 2I_(H). Thus, the voltages applied to theFET gates compensate or cancel the internal FET threshold and noisevoltages. The voltage around the loop formed by the gate of the two FETtransistors T₁″ and T₂″, the two diodes 20 and 22 and the capacitor S/Hsums to zero.

Referring now to FIG. 13, the switching sequence of the circuit in FIG.12 is illustrated for a single period equal to the frame rate. Twopulses are used for switching switches S₁ and S₂ and the switchingwaveforms are nested: S₂ is nested inside S₁. The antenna 30 (FIG. 3) isdisabled when switch S₁ is turned ON and enabled when switch S₁ isturned OFF The voltage across the capacitor S/H at time t₀ is recordedwhen switches S₁ and S₂ are opened and the antenna is enabled.

With these actions, the non-inverting voltage amplifier with the inputat FET T₁″ is enabled and the electro-thermal feedback loop is madeoperational. This leads to a new equilibrium between the scene, thedetector stage 14, and the intermediate stage 16. The temperature of theback-to-back diodes 20 and 22 changes and a voltage signal is producedto drive the voltage amplifier. This new voltage signal is in serieswith the recorded voltage across the capacitor S/H and the noise andthreshold voltages associated with each FET transistor T₁″ and T₂′.Summing all these voltage terms, the voltage V_(G)(t) applied to thegate of the FET voltage amplifier is given by, $\begin{matrix}\begin{matrix}{{V_{G}(t)} = {V_{T2} - V_{T1} + {E_{N1}(t)} - {E_{N2}(t)} + {\delta\quad{V_{G}(t)}} + {V_{S/H}\left( t_{o} \right)}}} \\{= {{E_{N1}(t)} - {E_{N1}\left( t_{O} \right)} - {E_{N2}\left( t_{O} \right)} + {E_{N2}\left( t_{O} \right)} + {\delta\quad{V_{IN}(t)}}}}\end{matrix} & (76)\end{matrix}$

The voltage recorded on the capacitor S/H cancels the local thresholdvariations. Additionally, noise voltages are recorded on the capacitorS/H and these will modify the noise in the circuit. The noisemodification is better recognized in the frequency domain which isrepresented by:V _(G)(ω)=E _(N1)(ω)└1−e ^(−iωt) ⁰ ┘−E _(N2)(ω)└−1−e ^(−iωt) ⁰ ┘+δV_(IN)(ω)  (77)

The spectral content of the voltage applied to the gate V_(G)(ω) is madeup of three terms, namely: two noise terms and a signal term. Each ofthe noise term is expressed as a difference between the noise value at“t” and “t_(o)”. The time dependence of the noise is unknown; however,it can be represented by its power spectral density. Using thisrepresentation, the noise contribution to the signal in Equation 77 canreadily be expressed as: $\begin{matrix}{{V_{G}(t)} = {{\delta\quad{V_{IN}(t)}} + \sqrt{{\int_{- \infty}^{\infty}{{{E_{N1}(\omega)}}^{2}\quad{\sin^{2}\left\lbrack \frac{\omega\quad t_{O}}{2} \right\rbrack}\quad{\mathbb{d}\omega}}} + {\int_{- \infty}^{\infty}{{{E_{N2}(\omega)}}^{2}\quad{\sin^{2}\left\lbrack \frac{\omega\quad t_{O}}{2} \right\rbrack}\quad{\mathbb{d}\omega}}}}}} & (78)\end{matrix}$

It is again evident from Equation 78 that the voltage amplifier noise ismodified by a sine-squared term and this term will suppress thecontribution of low frequency 1/f noise and double the power of thewhite noise. The reduction of the 1/f noise depends on the amplifierbandwidth and the time difference between sampling the noise and readingof the signal, or correlation. The time difference between reading thesignal and noise is t_(o)/2. Hence, noise terms with frequencies varyingslower than t_(o)/2 will be attenuated. Noise frequencies beyond thiswill be increased, depending on the amplifiers bandwidth.

The noise from the USSS electrical readout circuit is affected by CNCand electro-thermal feedback. Equation 77 provides an expression for theeffect of the CNC on the noise's spectral amplitude without includingany other effects. However, the noise is also modified by theelectro-thermal feedback and the voltage amplifier's frequency response.Both of these effects are incorporated into a model and an analyticalexpression is obtained that includes these effects. The analysis makesuse of superposition of the different frequency components of the noise.The specific values of the noise amplitude are not therefore thesevalues and are treated as algebraic variables. Once the linear analysisis completed with the noise amplitude, the results are transformed intoa power spectral density and integrated to compute the total RMS noisevalue. The noise power spectral density of the electrical circuits issomething that is routinely measured and the calculated analyticalresults can thus be numerically evaluated in terms of the experimentallymeasured noise power spectral density.

The effective total spectral noise voltage V_(NO)(ω), applied to the FETgate of the non-inverting voltage amplifier, without including any formof feedback, is given by Equation 77 {with the signal δV_(IN)(ω)removed) and is defined as,V _(NO)(ω)=E _(N1)(ω)└1−e ^(−iωt) ⁰ ┘−E _(N2)(ω)└1−e ^(−iωt) ⁰ ┘  (79)

Electro-thermal feedback effects this noise level and the noise voltageis modified to V_(N)(ω) from V_(NO)(ω) and these are related by theexpression: $\begin{matrix}\begin{matrix}{{{V_{NO}(\omega)} + {\delta\quad{E_{IN}(\omega)}}} = {{V_{NO}(\omega)} + {\frac{\partial\left\lbrack {\Delta\quad{\Phi_{IN}\left( T_{IN} \right)}} \right\rbrack}{\partial T_{IN}}\delta\quad{T_{IN}(\omega)}} -}} \\{\frac{\partial\left\lbrack {\Delta\quad{\Phi_{D}\left( T_{D} \right)}} \right\rbrack}{\partial T_{D}}\delta\quad{T_{D}(\omega)}} \\{= {{V_{NO}(\omega)} + {\frac{\partial\left\lbrack {\Delta\quad{\Phi_{IN}\left( T_{IN} \right)}} \right\rbrack}{\partial T_{IN}}\left\lbrack {{\delta\quad{T_{IN}(\omega)}} - {\delta\quad{T_{D}(\omega)}}} \right\rbrack}}} \\{= {V_{N}(\omega)}}\end{matrix} & (80)\end{matrix}$

The expression for δE_(IN)(ω) in Equation 80 was obtained from Equations14 and 50. Also, the temperature derivative ∂ΔΦ(T)/∂T of the potentialdifference across the temperature sensing diodes is the same for thedetector and intermediate stages 14 and 16. Thus, Equation 80 simplyreflects the fact that changing noise voltage on FET gate T₁″ willslightly change the FET amplifier current and this will cause a slightchange in the temperature of the intermediate stage 16. A detailedqualitative examination of the circuit in Figure I-12 reveals theeffects of electro-thermal feedback on the noise voltage amplitude.Specifically, the sequence of events that occurs if the noise amplitudeincreases at the FET gate T₁″ is as follows:

-   -   1. Noise at FET gate T₁″ gate increases.    -   2. Larger voltage on the gate reduces current flowing in the        channel of FET T₁″.    -   3. The output voltage V(out) becomes more negative.    -   4. With a bigger drop across the Drain source of FET T₁″ the        amplifiers quiescent power increases and heats up the        intermediate stage.    -   5. The temperature of the intermediate stage 16 increases        slightly.    -   6. The intermediate stage diode temperature sensor 22 decreases        its output voltage.    -   7. The voltage on the gate of FET T₁″ decreases slightly to        compensate for the increases in noise voltage.

If the noise voltage at the gate of FET T₁″ decreases, then the oppositewill occur for the aforementioned sequence. What is important to note isthat the sequence detailed above shows that electro-thermal feedbackreduces the amplitude of the noise voltage. This qualitative explanationis corroborated by the analysis that now follows.

Relating the noise with electro-thermal feedback [V_(N)(ω)] to the noisewithout electro-thermal feedback [V_(NO)(ω)] requires evaluatingEquation 80 and specifically requires computation of δT_(IN) and δT_(D),since ∂66 Φ(ω)/∂T is known from Equation 14. The relationship betweenδT_(IN) and δT_(D) is readily obtained from Equations 14. Usingsuperposition, the change in temperature of the intermediate stage interms of changes in the temperature of the detector stage is given byEquation 50 when δT_(S) is zero. After some algebra, the followingexpression is obtained: $\begin{matrix}{{\delta\quad T_{D}} = {\frac{\left\lbrack G_{2} \right\rbrack}{\left\lbrack {G_{D1} + G_{2} + {j\quad\omega\quad C_{D}}} \right\rbrack}\delta\quad T_{IN}}} & (81)\end{matrix}$

Change in quiescent heat delivered to the intermediate stage 14 by theinverting amplifier's FET gate noise voltage fluctuations is given inEquation 51 as I_(H)Z_(O)V_(N)(ω)g_(M). For the non-inverting amplifier,voltage gain is represented by Z_(O)g_(M). Making the propersubstitutions for voltage gain, the representation for the noise poweris given by δQ_(H)=[C_(D)/2C_(GD)]I_(H)V_(N)(ω). Substituting this forI_(H)Z_(O)V_(N)(ω))g_(M) in Equation 51, and after some rearrangement,the resulting expression is given by: $\begin{matrix}{{{{- \left\lbrack {G_{D2} + G_{2} + G_{3} + {j\quad\omega\quad C_{IN}}} \right\rbrack}\quad\delta\quad T_{IN}} + {G_{2}\delta\quad T_{D}} + {I_{H}{{V_{N}(\omega)}\left\lbrack \frac{C_{D}}{2C_{GD}} \right\rbrack}}} = 0} & (82)\end{matrix}$

Changes in the temperature of the intermediate stage 16 is readilycomputed in terms of the noise voltage by substituting Equation 81 intoEquation 82, and solving for δT_(IN) obtained is: $\begin{matrix}{{\delta\quad{T_{IN}(\omega)}} = \frac{I_{H}{{{V_{N}(\omega)}\left\lbrack \frac{C_{D}}{2C_{GD}} \right\rbrack}\left\lbrack {G_{D1} + G_{2} + {j\quad\omega\quad C_{D}}} \right\rbrack}}{{G_{2}\left\lbrack {G_{D1} + {j\quad\omega\quad C_{D}}} \right)} + {\left( {G_{D2} + G_{3} + {j\quad\omega\quad C_{IN}}} \right)\left( {G_{D1} + G_{2} + {j\quad\omega\quad C_{D}}} \right)}}} & (83)\end{matrix}$

Substituting Equation 81 for δT_(D) in Equation 80 and replacing δT_(IN)with Equation 83 an expression for the resulting FET gate noise voltagemodified by electro-thermal feedback is obtained in terms of the initialnoise voltage without feedback and it is given by: $\begin{matrix}\begin{matrix}{{V_{N}(\omega)} =} \\{\quad\frac{V_{NO}(\omega)}{\left\lbrack {1 + \frac{{- {I_{H}\left\lbrack \frac{C_{D}}{2C_{GD}} \right\rbrack}}\quad{\frac{\partial\left\lbrack {\Delta\quad{\Phi_{IN}(\omega)}} \right\rbrack}{\partial T_{IN}}\left\lbrack {G_{D1} + {j\quad\omega\quad C_{D}}} \right\rbrack}}{{G_{2}\left( {G_{D1} + {j\quad\omega\quad C_{D}}} \right)} + {\left( {G_{D2} + G_{3} + {j\quad\omega\quad C_{IN}}} \right)\left( {G_{D1} + G_{2} + {j\quad\omega\quad C_{D}}} \right)}}} \right\rbrack}}\end{matrix} & (84)\end{matrix}$

Electro-thermal feedback has decreased the noise amplitude and this isevident from the denominator of Equation 84, which is greater than one.The noise reduction depends on the size of the magnitude of thealgebraic expression in the denominator. However, it is evident that thebetter the thermal isolation between the detector 14 and intermediate 16stages [smaller G₂], and the intermediate 16 and heat bath 18 stages,[smaller G₃], the lower will be the noise from the readout circuit.

Thus, in designing a USSS based bolometer in accordance with the subjectinvention, care must be taken to minimize G₂, and G₃ so that maximumperformance can be achieved. Incorporating Equation 84 into Equation 77yields an expression for the noise and signal applied to the USSSnon-inverting FET readout amplifier with electro-thermal feedbackeffects included and it is given as: $\begin{matrix}{{V_{G}(t)} = {{\delta\quad{V_{IN}(t)}} + \sqrt{\int_{- \infty}^{\infty}{{{V_{N}(\omega)}}^{2}\quad{\sin^{2}\left\lbrack \frac{\omega\quad t_{O}}{2} \right\rbrack}\quad{\mathbb{d}\omega}}}}} & (85)\end{matrix}$

As previously mentioned, the CNC suppresses the low frequency 1/f noisecomponents since the sine squared term inside the integral of Equation85 provides an “ω²” term that cancels the divergence from the 1/f noise.The output noise voltage from the non-inverting voltage amplifierdepends on the transconductance and the output impedance and is givenas: $\begin{matrix}{{V_{O}(t)} = {g_{M}\quad{Z_{O}\left\lbrack {{\delta\quad{V_{IN}(t)}} + \sqrt{\int_{- \infty}^{\infty}{{{V_{N}(\omega)}}^{2}\quad{\sin^{2}\left\lbrack \frac{\omega\quad t_{O}}{2} \right\rbrack}\quad{\mathbb{d}\omega}}}} \right\rbrack}}} & (86)\end{matrix}$

The evaluation of the integral inside the square brackets requires useof exponential integrals and these have been tabulated but are not shownfor brevity.

Thus what has been shown and described is a sensor which includes a pairof back-to-back temperature sensing silicon diodes connected in anelectro-thermal feedback loop including a semiconductor amplifiercircuit located in an intermediate stage between a detector stage and aheat bath stage.

The invention being thus described, it will be obvious that the same maybe varied in many ways. Such variations are not to be regarded as adeparture from the spirit and scope of the invention, and all suchmodifications as would be obvious to one skilled in the art are intendedto be included within the scope of the following claims.

1. An ultra-sensitive electromagnetic radiation sensor assembly, comprising: a radiation detection sub-assembly; an intermediate stage sub-assembly; a heat bath sub-assembly; a first thermally responsive temperature sensing element collocated with a thermal absorber element in thermal contact with said radiation detector sub-assembly; a second thermally responsive temperature sensing element collocated with and in thermal contact with said intermediate stage sub-assembly; a temperature difference signal amplifier located in thermal contact with said intermediate stage sub-assembly together with said second temperature sensing element; first thermal isolation support means located between said radiation detection sub-assembly and said intermediate stage sub-assembly; second thermal isolation support means located between said intermediate stage sub-assembly and said heat bath sub-assembly; means connecting said first thermally responsive temperature sensing element and the second thermally responsive temperature sensing element so as to generate a temperature difference signal; and wherein said temperature difference signal is coupled to and amplified by said temperature difference signal amplifier.
 2. An ultra-sensitive sensor assembly according to claim 1 wherein said first and second temperature sensing elements are comprised of semiconductor diodes.
 3. An ultra-sensitive sensor assembly according to claim 1 wherein said first and second temperature sensing elements are comprised of p/n junction semiconductor diodes.
 4. An ultra-sensitive sensor assembly according to claim 1 wherein said first and second temperature sensing elements are comprised of silicon diodes.
 5. An ultra-sensitive sensor assembly according to claim 4 wherein said semiconductor diodes are comprised of p/n junction silicon diodes.
 6. An ultra-sensitive sensor assembly according to claim 5 wherein said diodes are connected in a series circuit relationship.
 7. An ultra-sensitive sensor assembly according to claim 5 wherein said semiconductor diodes are connected in a back-to-back series circuit relationship.
 8. An ultra-sensitive sensor assembly according to claim 1 wherein said radiation detection sub-assembly, said first temperature sensing element, and said thermal absorber element form a composite detector stage.
 9. An ultra-sensitive sensor assembly according to claim 1 wherein said intermediate stage sub-assembly, said second temperature sensing element, and said temperature difference signal amplifier form a composite intermediate bath stage.
 10. An ultra-sensitive sensor assembly according to claim 1 wherein said first thermal isolation support means comprises low thermal conductance bridge for supporting the radiation detection sub-assembly on the intermediate stage sub-assembly; and wherein said second thermal isolation support means comprises a low thermal conductance bridge for supporting the intermediate stage sub-assembly on the heat bath sub-assembly.
 11. An ultra-sensitive sensor assembly according to claim 10 and additionally including thermal radiation antenna means located adjacent the thermal absorber element of said detector sub-assembly and being coupled to said first temperature sensing element thereon.
 12. An ultra-sensitive sensor assembly according to claim 11 wherein said first and second temperature sensing elements are comprised of semiconductor diodes connected in back-to-back circuit relationship to said temperature difference signal amplifier means.
 13. An ultra-sensitive sensor assembly according to claim 12 wherein said temperature difference signal amplifier means includes at least one transistor coupled to said back-to-back diodes.
 14. An ultra-sensitive sensor assembly according to claim 13 wherein said temperature difference signal amplifier means includes a transistor coupled to each end of said back-to-back diodes.
 15. An ultra-sensitive sensor assembly according to claim 14 and additionally including circuit means for removing DC threshold voltage offsets and low frequency 1/f noise.
 16. An ultra-sensitive sensor assembly according to claim 15 wherein said circuit means comprises a sample and hold capacitor and switch means coupled between said back-to-back diodes and said signal amplifier means.
 17. A sensor assembly according to claim 16 wherein said transistors are coupled as inverting amplifiers to each end of said back-to-back diodes.
 18. A sensor assembly according to claim 17 and additionally including a transistor connected in cascode circuit relationship with one of said transistors coupled to said back-to-back diodes.
 19. A sensor assembly according to claim 16 wherein said transistors are coupled as non-inverting amplifiers to each end of said back-to-back diodes. 